Method and apparatus for the synchronous control of a serial interface

ABSTRACT

The present invention is directed to the synchronous control of a parallel interface. In particular, the present invention provides an interface between a serial communication link and parallel communication channels within an adapter that operate synchronously, and without requiring a data buffer. A data buffer may be provided between the parallel data channels of the adapter that operate synchronously with the serial data channel, and the adapter's host interface. The present application reduces the amount of memory that must be provided by the adapter, and eliminates delays caused by the provision of additional data buffers.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION

The present invention relates to the synchronous control of a serial computer interface.

With reference now to FIG. 1, a computer system utilizing an adapter in accordance with an embodiment of the present invention is illustrated. In addition to the adapter , the computer system generally includes a host computer , a host bus , a serial device , and a serial communication link . In general, the adapter interconnects the serial device to the host and in particular the host bus . Furthermore, the adapter converts the serial data stream received from the serial device over the serial communication link into a parallel data stream that is provided to the host over the host bus .

The host may include any type of computer system. For example, the host may include a Pentium™ processor based computer. The host bus may comprise any communication bus utilized for interconnecting a host computer (e.g., host ) to peripheral devices (e.g., serial device ). For example, the host bus may comprise a Peripheral Component Interface (PCI) bus. The serial device may include any device that communicates over a serial communication link, such as serial communication link . Accordingly, the serial device may include storage devices, such as hard disk drives, tape drives, optical storage devices, or solid state storage devices, including removable solid state storage devices, that utilize a serial communication protocol, such as the serial advanced technology attachment (SATA) protocol. Further, it should be appreciated that the serial device is not limited to storage devices, and can include devices such as input or output devices, and communication links to other computers.

As noted above, the adapter interconnects the serial device to the host . Furthermore, the host is generally interconnected to the adapter by a parallel communication bus . The adapter is interconnected to the serial device by the serial communication link . Accordingly, the adapter must translate between the parallel communication format used on the host bus and the serial communication format used on the serial communication link . However, this is not a simple serial to parallel conversion. In particular, the host bus having an adapter and a serial device interconnected thereto in accordance with the present invention will also have other devices that utilize the host bus for communications. Accordingly, the data transmission capacity of the host bus will vary. As a result, the adapter must be capable of buffering data transmitted between the adapter and the host over the host bus (or between the adapter and another host or device interconnected to the host bus ).

The adapter generally comprises a host interface , a transport layer , a link layer , and a physical layer . In general, the host interface and the various layers - of the adapter are interconnected to one another by parallel data channels . These parallel data channels may have different channel widths and operating frequencies. For example, the parallel channel interconnecting the host interface to the transport is, in accordance with an embodiment of the present invention, 128 bits wide and operates at a frequency of 75 MHZ. This width and operating frequency is useful in connection with a typical host bus , such as a PCI or PCI-X host bus, which have channel widths of up to 64 bits and operating frequencies of up to 133 MHZ. That is, the greater capacity of the parallel data channel between the host interface and the transport layer provides a pipeline that is large enough to receive data from the host bus without interposing delays in the transmission of data.

Continuing the present example, the parallel data channel interconnected the transport layer to the link layer may by 32 bits wide and have an operating frequency of 37.5 MHZ, to provide a data rate of 150 MB/s. This channel width and operating frequency may be selected to match the internal channel width and operating frequency of the transport layer . It will be noted that the data transfer rate of 1 GB/s provided by the parallel data channel between the host interface and the transport layer is greater than the 150 MB/s data rate provided by the parallel data channel interconnected the transport layer to the link layer . In order to accommodate these differing data transfer rates, and also to accommodate variations in the actual data rate available on the host bus , a data buffer (also referred to herein as transport-host interface buffer or first in first out buffer) is provided as part of the transport layer . In particular, the data buffer buffers data passed between the host interface and the transport layer by providing temporary data storage space to accommodate differences in the data transfer rate of the transport layer and the transfer rates available on the host bus during a transmission of data. For example, in accordance with an embodiment of the present invention, about one kilobyte of storage space is provided by the data buffer .

A clock may be included as part of the adapter to provide a synchronized timing signal to the layers -. The signal from the clock may be multiplied or divided by the various layers - as required.

Continuing the present example, the parallel data channel interconnecting the link layer to the physical layer may have a channel width of 10 bits and an operating frequency of 150 MHZ, for a data transfer rate of 150 MB/s, where each byte is encoded using 10 bits (i.e. is 10 B/8 B encoded). Accordingly, the parallel data channel interconnecting the link layer to the physical layer provides a data rate that matches the parallel data channel interconnecting the transport layer to the link layer , after accounting for the 10 B/8 B encoding (and decoding) performed in a 10 B/8 B coder provided as part of the link layer .

The physical layer interconnects the adapter to the serial device over the serial link . In accordance with an embodiment of the present invention, the serial link comprises a serial advanced technology attachment (SATA) serial link operating at a frequency of 1.5 GHz to provide a data rate of 150 MB/s (with each byte encoded as a 10 bit data word).

As can be appreciated from the present example, although different channel widths and frequencies may be selected, the data rates available on the parallel data channel interconnecting the transport layer to the link layer , the parallel data channel interconnecting the link layer to the physical layer , and the serial communication link interconnecting the physical layer to the serial device are matched. Accordingly, there is no need, nor is there provision for, a data buffer between the serial device and the transport layer of the adapter in accordance with embodiments of the present invention. In particular, the provision of matched data rates allows the transport layer , the link layer , the physical layer , and the serial device to be synchronized to one another in transferring data between the adapter and the serial device . In addition, by eliminating a buffer between the transport layer and the serial device , the adapter can occupy less area than a conventional adapter utilizing a data buffer between the transport layer and the serial device that is otherwise similar to an adapter in accordance with the present invention. Furthermore, by eliminating a buffer between the transport layer and the serial device , the pipeline delay encountered in connection with the transfer of data between the transport layer and the serial device is a constant value. In addition, the pipeline delay between the transport layer and the serial device of an adapter in accordance with the present invention is generally less than would be encountered in a conventional adapter because there is no need to pass data through such a buffer. The processing overhead associated with operation of an adapter in accordance with the present invention is also generally less than a conventional adapter because there is no need to control the operation of a buffer between the transport layer and the serial device .

In order to achieve the synchronous operation of the transport layer , the link layer , and the physical layer , with the transfer of data over the serial communication link between the adapter and the serial device , each of the aforementioned layers - must be capable of receiving data presented to the physical layer by the serial device over the serial communication link . In particular, the transport layer , the link layer , and the physical layer must be capable of receiving any data presented by the serial device , at least up to an amount equal to the system's receive latency size. The receive latency size is defined to be the amount of data that is sent from the serial device over the serial communication link between the time at which the adapter , and in particular the transport layer , determines that the receipt of data must be stopped and the time that the serial device is able to stop the transmission of data. Accordingly, this latency period includes the time required to send the signal to the serial device requesting that the transmission be stopped, and the time required for the serial device to act on the command. In general, because there is no buffer provided between the transport layer and the serial communication link , and because the pipeline delay between the transport layer and the physical layer is a constant, the receive latency size is a function of the available data capacity in the data buffer between the host interface layer and the transport layer . Accordingly, the adapter may signal the serial device to stop the transmission of data when a “high water mark” is reached in the data buffer .

In addition, the transfer of data between layers - of the adapter and the internal operation of those layers are synchronized to a common clock.

With reference now to FIG. 2, certain aspects of the link layer and the physical layer are shown in block diagram form. In general, frames of data are passed between the link layer and the physical layer , and between the physical layer and the serial device , as 10 B/8 B encoded data. Accordingly, the link layer includes a 10 B/8 B decoder and a 8 B/10 B encoder . In addition to performing 10 B/8 B coding functions, the link layer performs primitive coding functions. Accordingly, the link layer is provided with a primitive decoder and a primitive encoder . A scrambler is provided to implement a scrambling algorithm in connection with the communication protocol used between the adapter and the serial device . A cyclical redundancy check block is provided to detect problems in the transmission of data. Continuing the example given above, the transport and link may both operate at a frequency of 150 MHZ. In an embodiment of the present invention suitable for use with a 3.0 GHz serial link , the transport may operate at a frequency of 150 MHZ and the link may operate at a frequency of 300 MHZ. A link control state machine is provided for controlling the operation of the link layer .

With reference now to FIG. 3, aspects of the transport layer are shown in block diagram form. In general, the transport layer comprises a frame information structure decomposition block , a frame information structure send block , I/O command block engine , and I/O command block done engine . As noted above, the transport layer also includes a first in/first out data buffer at the interface between the transport layer and the parallel data channel interconnecting the transport layer to the host interface . The transport control block controls the operation of the various components and functions of the transport layer .

With reference now to FIG. 4, an overview of the steps taken in connection with the flow of data through an adapter in accordance with an embodiment of the present invention are illustrated. In general, at step , data or a control word is received by the physical layer as a serial data signal from the serial communication link . In accordance with an embodiment of the present invention, the data is 10 B encoded (i.e. an 8 bit byte is encoded using 10 bits to form a data word (dword)). At step , the data received is decoded using the 10 B/8 B decoder provided as part of the link layer. At step , primitives received are decoded using the primitive decoder .

At step , the data is placed on the link transport data bus (i.e. the parallel data channel interconnecting the link layer and the transport layer). Data is then presented to the transport (step ). The transport then provides the data to the host interface , with data buffering if necessary (step ).

From the description given above, it can be appreciated that data is received from the serial communication link and passed through to the transport layer , without any buffering of that data. Accordingly, the pipeline delay from the interface with the serial data link , through the physical layer and the link layer , up to the data buffer provided at the interface between the transport layer and the host interface layer , is constant. Furthermore, there is no possibility of variable delays, as there is no provision for data buffering, except for the data buffer at the interface between the transport layer and host interface .

With reference now to FIG. 5, a flow chart depicting the operation of an adapter in accordance with an embodiment of the present invention in connection with receiving data from a serial device is illustrated. Initially, at step , the serial device sends a control character to the adapter over the serial communication link , seeking to transmit a data frame. At step , a determination is made as to whether the data buffer (or transport-host interface buffer) has enough space to receive a number of words of a frame equal to the receive latency size of the system . As noted above, the receive latency size corresponds to an amount of data that is passed from a serial device to the adapter after a stop transmission command has been issued by the adapter . In particular, the receive latency size is a function of the number of clock cycles that elapse before a stop transmission signal can be generated by the adapter , provided to the serial device , and acted upon by the serial device . If the transport-host interface buffer is not capable of receiving a number of words equal to the receive latency size, the adapter signals that it is not ready to receive data (step ). The adapter then returns to step .

If the transport-host interface buffer does have enough room to receive a number of words of a frame equal to the receive latency size, handshaking procedures may be completed (step ). Next, a start of frame word is received (step ) followed by the first word of data (step ).

At step , a determination is made as to whether the transport-host buffer is at a high water mark (step ). In general, the high water mark corresponds to the receive latency size. If the buffer is at the high water mark, the device is signaled to stop transmitting (step ). The adapter may then continue to step .

If the buffer is not at the high water mark, or after the device has been signaled to stop transmitting at step , a determination is made as to whether the last word of the data frame being transmitted has been received (step ). If the last word of data within the data frame has been received, the transmission ends (step ).

If the last word of data within the data frame has not been received, the next word of data within the data frame is received (step ). Next, at step , a determination is made as to whether the adapter has signaled the serial device to stop transmitting data. If the adapter has signaled the serial device to stop transmitting data, a determination is made as to whether an amount of data received is equal to the receive latency size (step ). If the adapter has not signaled the serial device to stop transmitting data, the system returns to step . The system returns to step if at step it is determined that the amount of data that has been received since the signal to stop transmitting data was issued is equal the receive latency size (i.e. no more data will be received until a sign to recommence the transmission of data is sent to the device by the adapter ). If the amount of data received since the stop transmission signal was sent is equal to the receive latency size, the transmission will end (step ).

The foregoing discussion of the invention has been presented for purposes of illustration and description. Further, the description is not intended to limit the invention to the form disclosed herein. Consequently, variations and modifications commensurate with the above teachings, within the skill and knowledge of the relevant art, are within the scope of the present invention. The embodiments described hereinabove are further intended to explain the best mode presently known of practicing the invention and to enable others skilled in the art to utilize the invention in such or in other embodiments and with various modifications required by their particular application or use of the invention. It is intended that the appended claims be construed to include the alternative embodiments to the extent permitted by the prior art.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram depicting various operating layers of an adapter interconnected to a computer system in accordance with an embodiment of the present invention;

FIG. 2 is a block diagram of a link layer of an adapter in accordance with an embodiment of the present invention;

FIG. 3 is a block diagram of a transport layer of an adapter in accordance with an embodiment of the present invention;

FIG. 4 is a flow chart illustrating the steps taken in connection with the flow of data through an adapter in accordance with an embodiment of the present invention; and

FIG. 5 is a flow chart illustrating the operation of an adapter receiving data from a serial device in accordance with an embodiment of the present invention.

CLAIMS

1. A method for synchronously controlling a serial interface, comprising: generating a clock signal; receiving at a physical layer a serial data signal comprising a data frame including a first number of data bits; converting said serial data signal to a parallel data signal; providing said parallel data signal to a transport layer, wherein a pipeline delay between said physical layer and said transport layer is a predetermined number of cycles of said clock signal; generating in a transport layer a stop signal; and after generating said stop signal, receiving at said transport layer a number of bits corresponding to a receive latency size.

2. The method of claim 1, wherein said predetermined number of clock signals comprises an integer number of clock signals.

3. The method of claim 1, wherein said data frame is received from a first source.

4. The method of claim 3, wherein data included in said data frame is not buffered between said physical layer and said transport layer.

5. The method of claim 1, wherein said predetermined number of cycles of said clock signal is equal to said first length multiplied by a constant.

6. The method of claim 1, wherein said first length of said data frame is determined by a total number of bits included in said data frame.

7. The method of claim 1, wherein said physical layer receives said data frame from a first device, and wherein said transport layer provides said data bits included in said data frame to a host communication bus through a host interface.

8. The method of claim 7, wherein said device is an SATA device.

9. A computer device adapter, comprising: a host interface; a transport layer interconnected to said host interface layer; a link layer, wherein said transport layer and said link layer are interconnected by a parallel communication channel having a first width and a first operating frequency; and a physical layer, wherein said link layer and said physical layer are interconnected by a parallel communication channel having a second width and a second operating frequency, wherein said physical layer converts a signal received from said link layer over said parallel communication channel having a second width to a serial data signal having a third operating frequency, wherein said third operating frequency is a integer multiple of said first and second operating frequencies, wherein said first, second and third operating frequencies have an integral relationship to a clock signal, and wherein a frame of data having a first length is passed between said transport layer and said physical layer in a first number of clock signals.

10. The device of claim 9, wherein a clock signal provided to said transport layer has a frequency equal to said first operating frequency, and wherein a clock signal provided to said link layer is equal to said second operating frequency.

11. The device of claim 9, wherein said link layer, and said physical layer do not include a data buffer.

12. The device of claim 9, further comprising: a device; and a serial communication channel interconnecting said physical layer to said device, wherein said frame of data is passed between said transport layer and said device in said first number of clock cycles plus a number of cycles corresponding to a propagation delay.

13. The device of claim 12, wherein said physical layer and said device communicate over said serial communication channel according to an SATA protocol.

14. The adapter of claim 12, wherein said device is a SATA device.

15. The adapter of claim 14, wherein said SATA device comprises a computer data storage device.

16. The adapter of claim 9, wherein a data buffer is not interposed between said transport layer and said link layer or between said link layer and said physical layer.

17. The adapter of claim 9, wherein said host interface is interconnected to a host computer by a parallel communication channel.

18. A controller apparatus, comprising: a serial data channel operating at a first frequency and comprising first and second ends, wherein a frame of data containing a first amount of information is transferred by said serial data channel in a first number of clock cycles; a first parallel data channel operating at a second frequency and comprising first and second ends; and a physical layer, wherein said physical layer does not include a data buffer, wherein said first end of said first parallel data channel is synchronously interfaced to said second end of said serial data channel by said physical layer, wherein said frame of data containing said first amount of information is transferred by said first parallel data channel in a second number of clock cycles, and wherein a time period between providing a frame of data having said first amount of information to said first end of said serial data channel and receiving said frame of data having said first amount of information at said second end of said first parallel data channel is the same for any frame of data having said first amount of information.

19. The apparatus of claim 18, wherein said first number of clock cycles is an integer multiple of said second number of clock cycles.

20. The apparatus of claim 18, further comprising a data buffer at said second end of said first parallel data channel, wherein said data buffer accommodates differences in the data transfer rates of said first parallel data channel and a second parallel data channel.

21. The apparatus of claim 18, wherein a data transfer rate of said serial data channel is identical to a data transfer rate of said first parallel data channel.

22. A method for interfacing a host computer having a parallel communication bus to a serial device, comprising: providing a host interface comprising a parallel interface for passing data to and from said parallel communication bus of said host computer; providing transport layer logic interconnected to said host interface by a first parallel communication channel; providing link layer logic interconnected to said transport logic by a second parallel communication channel; and providing physical layer logic interconnected to said link logic by a third parallel communication channel, and having a serial interface for interconnecting said host computer to said serial device, wherein said second and third parallel communication channels operate synchronously with said serial interface.

23. The method of claim 22, wherein said serial interface operates asynchronously with said parallel communication bus.

24. The method of claim 22, further comprising: providing a serial device interconnected to said serial interface by a first serial communication channel, wherein said second and third parallel communication channels operate synchronously with said serial communication channel.

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