Voltage withstanding structure for a semiconductor device

ABSTRACT

A semiconductor device comprising: a semiconductor substrate, a dielectric film formed on the semiconductor substrate, a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric layer, and a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DESCRIPTION OF THE PRESENT INVENTION

The present invention will be described in detail with reference to the accompanying drawings.

FIG. 1A is a plan view showing a main part of a voltage withstanding structure of a semiconductor device according to a first embodiment of the invention.

FIG. 1B is a sectional view of the main part taken in line A—A in FIG. A.

The effect of a spiral thin film layer is the same in both cases where a high potential is applied to an inner island electrode with respect to an outer electrode (GND), and in contrast, the high potential is applied to the outer electrode. In the first embodiment, the former case is selected.

As seen from FIG. 1A, a planar semiconductor device has a high potential side electrode located at the center of the front surface, a low potential side electrode located outside the electrode and the spiral thin film layer which is located between the electrodes and and turned around the high potential side electrode three times so as to connect electrically the electrodes and to each other. The spiral thin film layer is constructed of a repetition of a first conduction type thin film layer and a second conduction type thin film layer .

As seen from FIG. 1B, an N-well layer is formed in the surface layer of a p-type substrate . In the surface layer of the N-well layer , an n-type high potential region , a p-type low potential region and a P-offset region are formed. Further, on the front surface side of the p-type substrate, the spiral thin film layer which is constructed of a repetition of the first conduction type thin film layer and the second conduction type thin film layer is formed through a dielectric oxide film . The areas of the spiral thin film layer located on line A—A are indicated by , and .

On the other hand, on the rear surface side of the p-type substrate , a rear surface side electrode is formed. The low potential side electrode is located at a chip end. A distortion layer is formed in a dicing plane of the end. Since the voltage blocking capability is lost in the distortion layer, the low potential side electrode and rear surface side electrodes are electrically connected to each other and fallen in GND in potential. By making the entire exposed surface of the chip end as a p-type layer in addition to the dicing plane , a stronger electrical connection can be made between the low potential side electrode and rear surface side electrode .

The spiral thin film layer can be made in such a manner that a non-doped polysilicon is doped with impurities of the first conduction type and the second conduction type to form the first conduction type thin film layer (region) and second conduction type thin film layer (region) alternately. Otherwise, the first conduction type polysilicon is doped at intervals with the second conduction type impurities to form the first conduction type thin film layers and second conduction type thin film layers alternately. Reference numeral denotes the inverted series connection state of p-n diodes where the first conduction type thin film layer is an n-type layer and the second conduction type thin film layer is a p-type layer. In FIG. 1A, a hollow portion refers to the first conduction type thin film layer and a hatched portion refers to the second conduction type thin film layer . For simplicity of illustration, the hatched portions to be inserted alternately in a direction indicated by an arrow X are not shown.

In this structure, when a positive potential Vs is applied to the high potential side electrode with respect to the low potential side electrode , the potential Vs is also applied to the end of the spiral thin film layer which is connected to the high potential side electrode so that a uniform potential distribution is formed in the spiral thin film layer.

FIG. 2A is a sectional view of the semiconductor device. FIG. 2B is a graph showing the potential distribution of the chip surface. The potential gradient is created on the surface of the P-offset layer.

FIG. 2A corresponds to the upper portion of FIG. B. FIG. 2B shows the potential distribution from the high potential side electrode to the low potential side electrode along line A—A in FIG. A. The respective areas of the spiral thin film layer taken in line A—A are indicated by numerals , and . The potentials applied to the spiral thin film layers (regions) , and are referred to as V, V and V, respectively. As seen, the potential from the high potential side electrode to the low potential side electrode has a constant average gradient. Therefore, the electric field in the depletion layers created in the N-well layer , P-offset layer and p-type substrate layer (not shown) is relaxed so that the semiconductor device can have a high withstand voltage.

Referring to FIG. 1A, the potential applied along the spiral thin film layer will be explained.

Assuming that the semiconductor device has a withstand voltage of e.g. 600 V, with respect to junctions serving as Zener diodes, the number of the p-n junctions in a reverse-blocked state is set at m=400, and the Zener voltage which is a breakdown voltage or withstand voltage of the junction diode is Vz=4 V for every diode. Thus, the whole voltage of the Zener diodes=4 V×400=1600 V. This gives a sufficient margin to the withstand voltage of 600 V of the semiconductor device so that the Zener diodes will not be broken down. Therefore, the semiconductor device will not be broken owing to heat generation. The voltage applied to a single Zener diode is as low as 600 V÷400=1.5 V. The potential lowers uniformly at the potential step of 1.5 V along the spiral thin film layer from the high potential side electrode to the low potential side electrode , thereby providing a uniform potential distribution.

Where the voltage Vz is set at 7 V, m is about 230 and the voltage applied to the single Zener diode is as low as about 2.6 V. Thus, the potential lowers uniformly at the potential step of 2.6 V along the spiral thin film layer from the high potential side electrode to the low potential side electrode , thereby providing a uniform potential distribution.

Since the concentration (concentrations of the first conduction type thin film layer and of the second conduction type thin film layer) of polysilicon constituting the Zener diodes is high, a variation in the voltage/current characteristic of the Zener diodes is small. In an actual measurement, the variation in the voltage shared by each Zener diode for a leak current is within 10%. The uniformity of the potential distribution along the spiral thin film layer can be also improved by increasing the concentration of polysilicon.

Thus, a stable potential distribution can be obtained along the spiral thin film layer without breaking down the Zener diodes, thereby increasing the withstand voltage of the semiconductor device.

In the embodiment shown in FIGS. 1A and 1B, the spiral thin film layer is turned three times around the inner high potential side electrode . However, the number of times of turn-around varies according to chip size and the-withstand voltage of the semiconductor . It should be noted that the larger number of times of turn-around is preferred because the uniformity of the potential distribution is improved on a line (e.g. line A—A) coupling the high potential side electrode with the low potential side electrode in line.

Although 400 Zener diodes was used in this embodiment, the number may be set so that the entire Zener voltage is not lower than the withstand voltage of the semiconductor device . The shape of the spiral thin film layer may be changed according to that of the electrode (e.g. shape of the high potential side electrode ) encircled thereby, and may be circular or polygonal. Further, although polysilicon was used as a material of the spiral thin film layer in this embodiment, a semiconductor material such as single crystal silicon, GaAs and SiC may be adopted. Furthermore, although a single spiral line was adopted from the start to end of the thin film layer , a plurality of spiral lines may be provided therefor.

In the embodiment hitherto described, a large number of p-n diodes were connected in the inverted series manner. An explanation will be given of an embodiment in which a large number of p-n diodes are connected in a forward series manner.

FIG. 3 is a plan view of the main part of the voltage withstanding structure of the semiconductor device according to the second embodiment of the invention. This embodiment is different from that shown in FIG. 1A in that the p-n junctions formed in the spiral thin film layer are alternately short-circuited by metallic films , and hence the p-n diodes serving as Zener diodes are connected in a forward-series manner. The metallic film may be made of a material such as aluminum which is usually used for the electrode of a device. The metallic film is formed on the p-n junction in a forward direction so that the p-n diode is placed in a reverse-blocked state as indicate by . Incidentally, although the metallic films are arranged alternately with respect to the p-n junctions in a direction of arrow Y, it is not shown.

In the first embodiment, the spiral thin film layer which is constructed of a repetition of Zener diodes according to the invention has been applied to the voltage withstanding structure of the horizontal type planar semiconductor device. However, it may be applied to the voltage withstanding structure of a vertical type planar semiconductor device in which a depletion layer expands horizontally from an active region of a chip. The embodiment in which the spiral thin film layer is applied to the vertical type semiconductor device.

FIG. 4 is a sectional view of the main part of a voltage withstanding structure in a semiconductor device according to the third embodiment of the invention.

As shown in FIG. 4, on the rear surface side of an n− layer , an n+ layer is formed. On the front surface side thereof, formed are a p-type well region which serves as a low potential region and p-type regions , and which is formed to surround the low potential region and serve as guard rings. At the chip end, a p-type region which serves as a high potential region is formed. In the p-type well which serves as the low potential region , an active region (occupied by a gate region and source region in an MOSFET) is formed. A low potential side electrode is formed on the low potential region , a high potential side electrode is formed on the high potential region , and a rear surface side electrode is formed on the n+ layer on the rear surface side. The rear surface side electrode and high potential side electrode are electrically connected to each other on a dicing plane .

The p-type guard ring regions , and surround the p-type well region in a ring shape. A spiral thin film which connects the high potential side electrode to the low potential side electrode is formed through a dielectric oxide film on a semiconductor substrate.

In such a structure, when a potential Vs is applied to the rear surface side electrode , the potential Vs is also applied between the high potential side electrode and low potential side electrode . Then, a leak current flows through the spiral thin film in a series connection of Zener diodes, thereby forming a potential distribution. This electric field due to the potential distribution uniformly expands the depletion layer formed in the semiconductor substrate to relax the concentration of an electric field, thereby improving the withstand voltage of the semiconductor device.

In a fourth embodiment of the invention, each of the first conduction type layer and the second conduction type layer which constitute the spiral thin film layer in FIGS. 1A and 1B is doped with impurities at 1×1018 cm−3 or higher. By highly doping these layers in this way, the p-n diode constituted by the first and the second conduction type thin film layer serves as a Zener diode. Further, by highly doping these layers, the variation in the voltage/current characteristic of the Zener diode when it is reverse-blocked can be suppressed so that the a uniform potential gradient can be formed along the spiral thin film layer. Further, by forming a group of Zener diodes in the spiral thin film layer, the temperature dependency of the potential distribution can be reduced as compared with the conventional resistive thin film layer.

In the semiconductor device according to the fourth embodiment of the invention, the dielectric oxide film though which the spiral thin film layer is formed on the semiconductor substrate has a thickness of 0.01-10 μm. If it is thinner than 0.01 μm, the spiral thin film may be brought into contact with the semiconductor substrate because of a variation in the manufacturing condition. On the other hand, if it is thicker than 10 μm, manufacturing it takes a long time. In addition, it is too thick so that the potential of the spiral thin film layer cannot be effectively conducted to the surface of the semiconductor substrate. Such a thing is not preferable for the device structure and necessarily leads to an increase in the production cost.

As described above, the spiral thin film layer according to the invention has a structure in which the Zener diodes are arranged repeatedly. This structure is designed so that the product (m×Vz) of the number m of the diodes in a reverse-blocked state and the Zener voltage Vz of each Zener diode is sufficiently larger than the withstand voltage of the semiconductor device. In this structure, when a voltage lower than the withstand voltage is applied between the high potential side electrode and the low potential electrode, a leak current Is in a reverse direction of the diodes flows through the spiral thin film, thereby forming a uniform potential distribution along the thin film layer. This moves carriers in the first conduction type thin film layer or second conduction type thin film layer so that the depletion layer is expanded to relax the concentration of an electric field, thereby improving the withstand voltage of the semiconductor device.]

By optimizing the impurity concentration of the first conduction type or second conduction type, number of the Zener diodes and material of the thin film layer, the invention can greatly reduce a variation of the leak current due to the size (width and length) of the thin film layer and a temperature change, thereby providing a stable withstand voltage as compared with the conventional field plate or spiral resistive layer.

FIG. 7 is a plan view of the main part of a voltage withstanding structure in the semiconductor device according to the fifth embodiment of the invention.

Four thin film layers are wound spirally, respectively. Each spiral thin film layer is composed of first conduction type thin film layers (areas) and second conduction type thin film layers (areas). This embodiment is different from the first embodiment shown in FIG. 1A in that a plurality of spiral thin film layers (first, second, third and fourth spiral thin film layer , , and ) are formed. Since the plurality of thin film layers are formed, even when any single thin film layer is cut, the other good thin film layer makes the potential distribution uniform, thereby improving reliability of the device withstand voltage.

The semiconductor device according to the fifth embodiment of the invention has the same section of its main part and the same potential distribution on the chip surface as those in FIGS. 2A and 2B, which are not explained here.

FIG. 8 is a sectional view of the semiconductor device according to a sixth embodiment of the invention. This embodiment is an application of the voltage withstanding structure according the first embodiment to a high withstand voltage horizontal-type NMOS (n-channel MOSFET).

As shown, an N-well region is formed in a p-type substrate , and in the surface layer thereof, a p− region and a P-offset region are formed. P-well regions and are also formed. Next, LOCOS's (Local Oxidation of Silicon) which are dielectric oxide films and are formed. Further, a gate electrode of polysilicon is formed through a gate oxide film (not shown), and polysilicon films , and a spiral thin film layer are formed on the dielectric oxide film . The spiral thin film layer is the same as that proposed in the first embodiment. As described previously, it is of course that the spiral thin film layer is composed of a large number of p-n diodes (e.g. Zener diodes).

Next, n+ regions , serving as a source region and n+ region serving as a drain region are formed. Simultaneously, n+ regions (not shown) of the spiral thin film layer are also formed. Further, the polysilicon films and which are a field plate are formed as n type low-resistive layers.

In order to make contacts, p+ regions , and are formed, and p+ region (not shown) of the spiral thin film layer is also formed.

The substrate surface is covered with a dielectric film of PSG (phosphorus glass) (not shown). After contact holes are made, source electrodes , and a drain electrode are formed, and a rear side electrode is formed on the rear surface.

The high withstand voltage horizontal-type NMOS is structured so that in the “ON” state, an electron flow which is a main current flows from the source side (n+ regions , ) to drain side (n+ region ) in an active region . Since the spiral thin film layer is formed above the active region through which the main current flows, the potential distribution from the drain side to the source side in a blocked state can be made uniform, thereby improving reliability of the device withstand voltage. In addition, the source-drain distance can be shortened to reduce the “on” resistance and decrease the area occupied by the device.

FIG. 9 is a sectional view of the semiconductor device according to a seventh embodiment of the invention. This embodiment is an application of the voltage withstanding structure according the first embodiment to a high withstand voltage horizontal-type PMOS (p-channel MOSFET). Although the structure is not shown in detail, a spiral thin film layer is formed above an active region as in the case of FIG. .

As shown in FIG. 9, the P-channel MOS has a semiconductor substrate with a dielectric film layer formed on the semiconductor substrate . The references HV, G, and GND indicate a gate electrode , a source electrode , and a drain electrode , respectively, and a rear side electrode is formed on the rear surface of the device. The gate or first electrode and the source or second electrode are separated from each other on the dielectric film . The spiral thin film layer is formed on the dielectric film and surrounds the first electrode . The spiral thin film layer also and has both ends connected to the first electrode and the second electrode , respectively. As described previously, a plurality of p-n diodes (not shown) are formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer. Further, as shown in FIG. and recited in claim , a first region of a first conduction type is located in a surface layer of the semiconductor substrate . A second region and a third region , both of a second conduction type, are separated from each other and are located in a surface layer of the first region . A fourth region of the second conduction type is also in the surface layer of the first region , but is between the second region and the third region . As shown, the fourth region is apart from the second region , but comes into contact with the third region . The first electrode is formed on one of a surface layer of the second region and a region of the first region between the second region and the third region . Meanwhile, the second electrode is connected to the third region . Since FIG. 9 shows a P-channel MOS and the first electrode is a gate electrode, the region below the first electrode is a channel region and can be specified as a N-type of the channel region of the P-channel. Accordingly, the second region and the third region , which abut to the source electrode and the drain electrode , respectively, can be specified as a P-type. Furthermore, since the fourth region is defined in claim to be of the second conductor type, the fourth region can be specified as a P-type. This embodiment can also have the same advantage as in the sixth embodiment.

In accordance with the invention, the spiral thin film layer is turned around an island region externally so as to connect electrically a high potential region and a low potential region to each other, and is constructed of a repetition of Zener diodes. This provides the following effects.

The withstand voltage in the voltage withstanding structure mainly depends on the number of the Zener diodes, and does not greatly depend on the width of the thin film layer. This permits the width of the spiral thin film layer to be made constant for the chips with the different sizes and with the same withstand voltage. Therefore, where devices with the same withstand voltage are manufactured, the production cost can be greatly reduced as compared with the conventional resistive thin film layer (field plate or spiral resistive thin film layer).

Since the reverse withstand voltage of the Zener is used, the temperature dependency of the withstand voltage of the voltage withstanding structure is small, thereby permitting the withstand voltage to be provided stably.

The polysilicon of the spiral thin film layer is heavily doped with impurities at 1×1018 cm−3 or higher so that the voltage/current characteristic of each of the Zener diodes can be made uniform. This makes the potential gradient uniform from the high potential region to the low potential region, thereby providing a higher withstand voltage.

Provision of a plurality of thin film layers improves reliability for the withstand voltage of the device.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a plan view showing a main part of a voltage withstanding structure of a semiconductor device according to a first embodiment and a fourth embodiment of the invention.

FIG. 1B is a sectional view of the main part taken in line A—A in FIG. A.

FIG. 2A is a sectional view of the semiconductor device.

FIG. 2B is a graph showing the potential distribution of the chip surface.

FIG. 3 is a plan view of a withstanding structure of a semiconductor device according to a second embodiment of the invention.

FIG. 4 is a plan view of a withstanding structure of a semiconductor device according to a third embodiment of the invention.

FIG. 5 is a graph showing the voltage/current of a Zener diode using polysilicon.

FIG. 6A is a schematic view of the distribution of an electric field along the spiral thin film layer.

FIG. 6B is an enlarged view of FIG. 6A along the spiral thin film layer and a schematic view of a spiral thin film layer.

FIG. 6C is a graph showing the potential distribution along the spiral thin film layer.

FIG. 7 is a plan view of the main part of a voltage withstanding structure according to a fifth embodiment of the invention.

FIG. 8 is a sectional view of the main part of a semiconductor device according to a sixth embodiment of the invention.

FIG. 9 is a sectional view of the main part of a semiconductor device according to a seventh embodiment of the invention.

FIG. 10A is a sectional view of the main part showing a composite structure of a Double RESURF structure and a resistive field plate structure of the conventional voltage withstanding structure.

FIG. 10B is a graph showing the potential distribution of the conventional voltage withstanding structure shown in FIG. A.

FIG. 11 is a view of enlargement of a depletion layer.

FIG. 12 is a plan view of the main part of a spiral thin film resistive layer in a conventional voltage withstanding structure.

This application is a divisional application of application Ser. No. 09/494,995, filed on Jan. 31, 2000, now U.S. Pat. No. 6,603,185.

CLAIMS

1. A semiconductor device comprising: a semiconductor substrate; a dielectric film formed on the semiconductor substrate; a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric film; a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer; a first region having a second conduction type in a surface layer of the semiconductor substrate, the first region connected to the first electrode; a second region having the second conduction type, the second region apart from the first region in the surface layer of the semiconductor substrate, the second region connected to the second electrode; and a third region having the second conduction type, the third region formed in a ring-shape in the surface layer of the semiconductor substrate between the first region and the second region, the third region surrounding the first region; and wherein the semiconductor substrate is of a first conduction type.

2. A semiconductor device comprising: a semiconductor substrate; a dielectric film formed on the semiconductor substrate; a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric film; a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer; a first region having a first conduction type in a surface layer of the semiconductor substrate, a second region having a second conduction type in a surface layer of the first region; a third region having the second conduction type in the surface layer of the first region, the third region apart from the second region; and a fourth region having the second conduction type in the surface layer of the first region between the second region and the third region, the fourth region apart from the second region, the fourth region coming into contact with the third region; wherein the first electrode is formed on one of a surface layer of the second region and a region on the first region between the second region and the third region, wherein the second electrode is connected to the third region.

3. The semiconductor device as claimed in claim 2, wherein the semiconductor substrate is formed by the second conduction type.

4. A semiconductor device comprising: a semiconductor substrate; a dielectric film formed on the semiconductor substrate; a first electrode and a second electrode separated from each other on the dielectric film; a spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, the spiral thin film layer surrounding the first electrode, the thin film layer being formed on the dielectric film; a plurality of p-n diodes formed in series in the spiral thin film layer along a longitudinal direction of the spiral thin film layer; a first region having a first conduction type in a surface layer of the semiconductor substrate, a second region having the first conduction type in a surface layer of the first region, the second region connected to the first electrode; a third region having a second conduction type in the surface layer of the first region, the third region apart from the second region, the third region connected to the second electrode; and a fourth region having the second conduction type in the surface layer of the first region between the second region and the third region, the fourth region apart from the second region, the fourth region coming into contact with the third region; wherein the semiconductor substrate is formed by the second conduction type.

5. A semiconductor device comprising; a semiconductor substrate; a dielectric film formed on the semiconductor substrate; a first electrode and a second electrode separated from each other on the dielectric film; a plurality of spiral thin film layers, each spiral thin film layer having both ends connected to the first electrode and the second electrode, respectively, each spiral thin film layer surrounding the first electrode, each spiral thin film layer being formed on the dielectric film; and a plurality of p-n diodes formed in series in each spiral thin film layer along a longitudinal direction of the spiral thin film layer.

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