Semiconductor device with reduced parasitic capacitance between impurity diffusion regions

ABSTRACT

A first layer is formed on an underlying substrate having a surface layer made of semiconductor of a first conductivity type. The first layer is made of semiconductor having a resistance higher than that of the surface layer. A first impurity diffusion region of a second conductivity type is formed in a partial surface region of the first layer. The first impurity diffusion region does not reach the surface of the underlying substrate. A second impurity diffusion region of the first conductivity type is disposed in the first layer and spaced apart from the first impurity diffusion region. The second impurity diffusion region reaches the surface of the underlying substrate. A separation region is disposed between the first and second impurity diffusion regions. The separation region comprises a trench formed in the first layer and dielectric material disposed at least in a partial internal region of the trench.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 is a plan view of a semiconductor photo sensor according to the first embodiment of the invention. A trench having a plan shape in conformity with the outer periphery of a square is disposed in the surface layer of a semiconductor substrate. A separation region interconnects the centers of the opposing two sides of a square defined by the trench to partition the inside of the trench into four regions. The distal ends of the separation region abut on the sidewall of the trench .

Cathode regions to are disposed in the four regions partitioned by the separation region . Each of the cathode regions to is disposed spaced apart from the trench and separation region by a certain distance. The surfaces of the cathode regions to and separation region are covered with an antireflection film as will be later described. Electrode lead openings to are formed through the antireflection film in correspondence with and inside of the cathode regions to

An anode lead region surrounds the outside of the trench . Another trench surrounds the outside of the anode lead region .

FIG. 2 is a cross sectional view taken along one-dot chain line A—A shown in FIG. . In the surface layer of a p-type silicon substrate having an impurity concentration of 1×1014 to 1×1018 cm−3, p-type impurities are doped to form a p-type high impurity concentration layer having a peak concentration of about 1×1017 cm−3. On this p-type high impurity concentration layer , a p-type epitaxial layer is formed which has a thickness of about 10 to 20 μm and a p-type impurity concentration equal to or lower than 1×1014 cm−3 on its upper surface side. On the p-type epitaxial layer , an n-type epitaxial layer is formed having an impurity concentration of about 5×1015 cm−3 and a thickness of 0.8 to 2 μm.

On the surface of the n-type epitaxial layer , a field oxide film is formed to define a plurality of active regions.

In the n-type epitaxial layer in the central active region shown in FIG. 2, the n-type cathode regions and are formed. Although not drawn in FIG. 2, the cathode regions and are also formed in this active region. The cathode regions -are n-type impurity diffusion regions doped with phosphorous and have an impurity concentration of 1×1015 to 1×1020 cm−3. The cathode regions to reach the upper surface of the p-type epitaxial layer . The structure that the cathode regions to do not reach the upper surface of the p-type epitaxial layer may also be applied.

In the n-type epitaxial layer between the cathode regions and , the separation region is formed. The separation region is a p-type impurity diffusion region doped with boron and has an impurity concentration of 1×1016 to 1×1020 cm−3. The separation region electrically separates the cathode regions and and prevents leak current from flowing therebetween.

It is preferable that the depth of the separation region is made equal to or shallower than that of the cathode regions -The antireflection film is formed on the surface of the active regions in which the cathode regions and are formed. The antireflection film has the two-layer structure of a silicon oxide film and a silicon nitride film to lower the reflectivity relative to light in the reception wavelength range.

The anode lead regions are formed in the active regions adjacent to the active regions in which the cathode regions and are formed. The anode lead region is a p-type impurity diffusion region doped with boron and has an impurity concentration of 1×1016 to 1×1020 cm−3. The anode lead region extends from the upper surface of the n-type epitaxial layer to the p-type high impurity concentration layer . As will be later described, the anode lead region is formed by two ion implantation processes, one before forming the n-type epitaxial layer and the other after forming the n-type epitaxial layer .

A reverse bias voltage is applied between the cathode region and anode lead region and between the cathode region and anode lead region .

The trench is formed between the active regions in which the cathode regions and are disposed and the active region in which the anode lead region is disposed. The other trench is formed to surround the anode lead region together with the trench . The trenches and extend to the depth slightly shallower than the boundary between the p-type high impurity concentration layer and p-type epitaxial layer and have a width of about 1 μm. A silicon oxide film having a thickness of about 0.3 μm is formed on the bottom and inner sidewalls of the trenches and . A filler of polysilicon is buried in the trenches and .

A channel stopper diffusion region highly doped with boron is formed in a partial region of the p-type epitaxial layer contacting the trenches and . The n-channel stopper diffusion region has a boron impurity concentration of 1×1016 to 1×1018 cm−3. The n-channel stopper diffusion region reduces leak current flowing along the bottom and sidewall of the trench .

In the photo sensor of the first embodiment described above, photodiodes are constituted of the p-type epitaxial layer and p-type high impurity concentration layer as the anode and the cathode regions and as the cathodes. The p-type epitaxial layer having a high resistance is disposed between the cathode region and p-type high impurity concentration region . Parasitic capacitance between the cathode and anode can therefore be reduced more than the conventional photo sensor shown in FIGS. A and B in which the cathode region and the p-type substrate (anode) contact directly.

The trench is disposed between the cathode region and anode lead region . Since the dielectric constant of the silicon oxide film disposed in the trench is lower than that of silicon, parasitic capacitance therebetween can be reduced. The trench is disposed spaced apart from the anode lead region by a certain distance in the substrate in-plane direction. Therefore, parasitic reduction effects can be enhanced. Instead of the silicon oxide film, other films may be used which are made of dielectric material having a dielectric constant lower than that of silicon.

FIG. 3 is a graph showing an impurity concentration distribution along a depth direction at the side of the trench shown in FIG. . The abscissa represents an impurity concentration and the ordinate represents a depth. A broken line indicates the concentration of n-type impurities doped when the n-type epitaxial layer is formed. A solid line indicates the concentration of p-type impurities doped when the p-type epitaxial layer is formed. A solid line indicates the concentration of p-type impurities doped when the n-channel stopper diffusion region is formed.

A cross point between the broken line and solid line corresponds to an interface between the n-type epitaxial layer and p-type epitaxial layer . The p-type impurities doped to form the n-channel stopper diffusion region are left in the p-type epitaxial layer and do not diffuse into the n-type epitaxial layer . Namely, the n-channel stopper diffusion region is disposed spaced apart from the n-type epitaxial layer by a certain distance in the depth direction, and formed in the p-type epitaxial layer . As a result, an increase in parasitic capacitance between the cathode region and n-channel stopper diffusion region can be suppressed.

The trench may be made deeper to dispose the n-channel stopper diffusion region only near at the bottom of the trench . With this structure, parasitic capacitance between the cathode region and n-channel stopper diffusion region can be reduced further. To realize this structure, the trench shown in FIG. 2 may be made deeper than the trench .

Reverting to FIG. 1, an n-channel stopper diffusion region is disposed in an area including the interface between the separation region and trench .

FIG. 4 is a cross sectional view taken along one-dot chain line A—A shown in FIG. . The separation region is disposed in the active region and does not extend under the field oxide film . The n-channel stopper diffusion region is disposed under the field oxide film between the separation region and trench . The n-channel stopper diffusion region is a p-type impurity diffusion region doped with boron and has an impurity concentration of about 1×1017 cm−3.

The n-channel stopper diffusion region can reduce leak current flowing between adjacent cathode regions, e.g., cathode regions and , via the side area of the trench shown in FIG. .

FIG. 5 is a plan view of a photo sensor according to the second embodiment. In the first embodiment shown in FIG. 1, the trench is singularly disposed between the cathode regions -and anode lead region , whereas in the second embodiment, double trenches A and B are disposed. Namely, two trenches are disposed along a direction of separating the cathode regions -and anode lead region . The other structures are the same as those of the photo sensor of the first embodiment.

By disposing two trenches, parasitic capacitance between the cathode regions -and anode lead region can be reduced further. Three or more trenches may be disposed.

FIG. 6 is a plan view of a photo sensor according to the third embodiment. In the first embodiment shown in FIG. 1, the width of the trench is about 1 μm, whereas in the third embodiment, the width of a trench C disposed between the cathode regions -and anode lead region is made wider. The distance between the cathode regions -and anode lead region is therefore longer than that of the photo sensor of the first embodiment.

The other structures are the same as those of the photo sensor of the first embodiment shown in FIG. . Namely, the width of the trench surrounding the outer periphery of the anode lead region is the same as that of the trench of the photo sensor of the first embodiment.

By broadening the width of the trench C wider than that of the trench of the first embodiment, parasitic capacitance between the cathode regions -and anode lead region can be reduced. If the silicon oxide film formed on the bottom and inner sidewall of the trench C is made thicker, parasitic capacitance reduction effects can further be enhanced. A silicon oxide film may be filled in the whole inner space of the trench C.

FIG. 7 is a plan view of a photo sensor according to the fourth embodiment. In the photo sensor of the first embodiment shown in FIG. 1, the separation region is the p-type impurity diffusion region as shown in FIG. 2, whereas in the fourth embodiment, a separation region A is constituted of a trench and a filler filled in the trench. A trench constituting the separation region A is branched from the trench disposed between the cathode regions -and anode lead region . By using the separation region A of the trench structure, parasitic capacitance between the cathode regions -and separation region of the first embodiment can be reduced.

FIG. 8 is a plan view of a photo sensor according to the fifth embodiment. In the first embodiment shown in FIG. 1, the trench disposed between the cathode region and anode lead region is continuous with the trench disposed between the adjacent cathode region and anode lead region , and the distal end of the separation region abuts on the side wall of the trench .

In the fifth embodiment, a separation region B between two adjacent cathode regions, e.g., cathode regions and , reaches the anode lead region . Namely, the distal end of the separation region B abuts on the sidewall of the anode lead region . Therefore, a trench D between the cathode region and anode lead region and a trench E between the cathode region and anode lead region are separated by the separation region B.

The distal ends of the trenches D and E abut on the sidewall of the separation region B. A trench F between the cathode region and anode lead region and a trench G between the cathode region and anode lead region have the structure same as that of the trenches D and E. The other structures are the same as those of the photo sensor of the first embodiment.

In the first embodiment, leak current may flow between the cathode regions and via the side area of the trench . In the fifth embodiment, the trench D between the cathode region and anode lead region and the trench E between the cathode region and anode lead region are separated by the separation region B. It is therefore possible to prevent leak current from flowing along the side area of the trench .

FIG. 9 is a plan view of a photo sensor according to the sixth embodiment. In the fifth embodiment shown in FIG. 8, the trench D is singularly disposed between the cathode region and anode lead region , whereas in the sixth embodiment, a trench H corresponding to the trench D of the fifth embodiment has a duplicate structure along the direction of separating the cathode region and anode lead region . Other trenches I, J and K have also the duplicate structure. The other structures are the same as those of the photo sensor of the fifth embodiment shown in FIG. .

By making the trench D disposed between the cathode region and anode lead region have the duplicate structure, parasitic capacitance between these regions and can be reduced. Next, with reference to FIGS. 10A to G, a method of manufacturing the photo sensor of the first embodiment will be described. In the method to be described below, bipolar transistors for amplifying photocurrent generated by the photo sensor are formed at the same time on the same substrate as that of the photo sensor. As show in FIG. 10A, boron ions are implanted into the surface layer of a p-type silicon substrate having a resistivity of about 40 Ω·cm to thereby form a p-type high impurity concentration layer having the surface impurity concentration of about 1×1019 cm−3. On this p-type high impurity concentration layer , a high resistance p-type epitaxial layer is formed by chemical vapor deposition (CVD), the layer having a surface impurity concentration of about 1×1014 cm−3.

Boron ions are implanted into a partial region of the p-type epitaxial layer to form an anode lead buried region . The anode lead buried region reaches the p-type high impurity concentration layer and corresponds to the anode lead region shown in FIG. 2 in the p-type epitaxial layer . The anode lead buried region has an impurity concentration of 1×1016 to 1×1018 cm−3.

As shown in FIG. 10B, phosphorous ions are implanted in a partial region of the p-type epitaxial layer to form an n-type p-channel stopper diffusion region . The p-channel stopper diffusion region is disposed in the p-type epitaxial layer and does not reach the p-type high impurity concentration layer . The phosphorous concentration in the p-channel stopper region is 1×1016 to 1×1018 cm−3. The phosphorous concentration is controlled so that a sufficient breakdown voltage is ensured between the p-type high impurity concentration layer and p-channel stopper diffusion region and between the collector region of a pnp transistor to be formed in the p-channel stopper diffusion region and the p-channel stopper diffusion region .

Next, antimony ions are implanted into a partial region of the p-type epitaxial layer to form an n-type buried diffusion region . At the same time, an n-type buried diffusion region continuous with the p-channel stopper diffusion region is formed. The antimony concentration of the n-type buried diffusion regions and is 1×1018 to 1×1020 cm−3.

Boron ions are implanted into a partial region of the surface layer of the p-channel stopper diffusion region to form a p-type buried diffusion region . At the same time, boron ions are implanted into a region corresponding to the separation region shown in FIG. 1 to form a lower separation region. The boron concentration of the p-type buried diffusion region and lower separation region is 1×1016 to 1×1018 cm3.

On the p-type epitaxial layer , an n-type epitaxial layer is formed by CVD to a thickness of 0.8 to 2 μm. An n-type impurity concentration of the n-type epitaxial layer is about 5×1015 cm−3.

Boron ions are implanted into a partial region of the n-type epitaxial layer in contact with the p-type buried diffusion region to form a p-type well . At the same time, boron ions are implanted into a partial region of the n-type epitaxial layer in contact with the anode lead buried region to form an upper anode lead region . The boron concentration of the p-type well and upper anode lead region is 1×1016 to 1×101 cm−3. The anode lead buried region and upper anode lead region constitute the anode lead region shown in FIG. . As shown in FIG. 10C, on the surface of the n-type epitaxial layer , a mask pattern for local oxidation of silicon (LOCOS) is formed. The mask pattern has a two-layer structure of a silicon oxide film and a silicon nitride film.

Boron ions are implanted into the area where the n-channel stopper diffusion region shown in FIG. 1 is formed. The boron concentration of the n-channel stopper diffusion region is about 1×1017 cm−3. Since boron ions are implanted before LOCOS, the n-channel stopper diffusion region is also disposed under the field oxide film to be formed at a later process.

By using the mask pattern as a mask, the surface of the n-type epitaxial layer is locally oxidized. As shown in FIG. 10D, a field oxide film is therefore formed and active regions are defined. The thickness of the field oxide film is about 600 nm. Next, the trenches and shown in FIG. 1 are formed. At the same time, a trench is formed in the boundary area between the active region where a pnp transistor is disposed and the active region where an npn transistor is disposed.

After the trenches are formed, boron ions are implanted to form the n-channel stopper diffusion region shown in FIG. . The boron concentration is 1×1016 to 1×1018 cm−3.

A silicon oxide film is formed covering the inner surface of the trenches , and and the substrate surface. A polysilicon film is formed burying the inside of the trenches , and . The silicon oxide film and polysilicon film are etched back to leave the silicon oxide film and polysilicon film only in the trenches. A silicon oxide film is formed over the whole surface of the substrate to cover the upper surface of the polysilicon film in the trenches with the silicon oxide film.

An antireflection film is formed over the whole surface of the substrate. The antireflection film has a two-layer structure of a silicon oxide film and a silicon nitride film. These layers are formed, for example, by thermal oxidation and CVD. Boron ions are implanted into the n-type epitaxial layer above the lower separation region to form an upper separation region . The boron concentration is 1×1016 to 1×1020 cm−3. The lower separation region and upper separation region constitute the separation region shown in FIG. .

Next, phosphorous ions are implanted to form a cathode region . The phosphorous concentration is 1×1015 to 1×1020 cm−3. Arsenic or antimony may be used instead of phosphorous. The impurity concentration of the separation region and cathode region is properly determined by considering the sensitivity and response speed of a photodiode.

Processes up to the structure shown in FIG. 10E will be described. An opening is formed through the antireflection film at the position where an electrode is formed. A first layer polysilicon film is formed over the whole substrate surface to a thickness of about 300 nm. This polysilicon film is patterned to leave a first layer polysilicon film which covers the opening formed through the antireflection film . The polysilicon film is also left on the antireflection film which covers the surface of the cathode region

Phosphorous ions are implanted into the collector region of the npn transistor via the polysilicon film . The phosphorous concentration is about 1×1019 cm−3. The collector region reaches the n-type buried diffusion region . At the same time, an n-type lead region is formed reaching the n-type buried diffusion region .

Boron ions for forming an external base are implanted into the polysilicon film covering the active region in which the npn transistor is disposed. Phosphorous ions for forming an external base are implanted into the polysilicon film covering the active region in which the pnp transistor is disposed. The boron and phosphorous concentration is about 1×1019 cm−3.

An interlayer insulating film made of silicon oxide is formed over the whole surface of the substrate. Emitter windows and are formed through the interlayer insulating film . Ions are implanted via the emitter windows to laterally connect the inter and outer bases. Sidewall spacers are formed on the inner sidewalls of the emitter windows and

Next, ions for forming an inner base are implanted via the emitter windows and into the surface layer of the n-type epitaxial layer . Boron ions are implanted into the inner base of the npn transistor, and phosphorous ions are implanted into the inner base of the pnp transistor. The boron and phosphorous concentration is about 1×1018 cm−3.

After ions are implanted, an annealing process is performed. With this annealing process, boron ions in the polysilicon film diffuse into the surface layer of the n-type epitaxial layer to form an outer base . Similarly, phosphorous ions in the polysilicon film diffuse into the surface layer of the p-type well to form an outer base .

As shown in FIG. 10F, a second layer polysilicon film is formed on the interlayer insulating film . Phosphorous ions are implanted into a partial region of the polysilicon film where the npn transistor is disposed, and boron ions are implanted into a partial region where the pnp transistor is disposed. The phosphorous and boron concentration is 1×1019 to 1×1020 cm−3. The polysilicon film is patterned to leave emitters and made of polysilicon in the emitter windows and . Impurities in the emitters and are diffused by an annealing process into the surface layer of the n-type epitaxial layer .

Openings are formed through the interlayer insulating film in order to form lead electrodes for the collector, base and emitter of a transistor, the cathode and anode of a photodiode and the like. A first layer aluminum electrode is formed in these openings. On the first layer interlayer insulating film , a second layer interlayer insulating film made of silicon oxide is formed. An opening is formed through the second layer interlayer insulating film in order to form a lead electrode for the base of the npn transistor. A second layer aluminum electrode is formed in this opening. A cover film made of silicate glass and silicon nitride is formed on the second interlayer insulating film .

As shown in FIG. 10G, an opening is formed through the three layers from the cover film to first layer interlayer insulating film in the photodiode light reception area. At this time, the first polysilicon film covering the surface of the antireflection film serves as an etching stopper. After the opening is formed, the polysilicon film on the antireflection layer is removed.

With this manufacture method, the lower separation region is formed at the same time when the p-type buried diffusion region is formed. The upper anode lead region is formed at the same time when the p-type well is formed. An increase in the number of manufacture processes can therefore be suppressed as much as possible.

The present invention has been described in connection with the preferred embodiments. The invention is not limited only to the above embodiments. It is apparent that various modifications, improvements, combinations, and the like can be made by those skilled in the art.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a plan view of a photo sensor according to a first embodiment.

FIG. 2 is a cross sectional view of the photo sensor according to the first embodiment.

FIG. 3 is a graph showing an impurity concentration distribution along a depth direction at the side of a trench of the photo sensor of the first embodiment.

FIG. 4 is a cross sectional view showing a junction area between the trench and a separation region of the photo sensor of the first embodiment.

FIG. 5 is a plan view of a photo sensor according to a second embodiment.

FIG. 6 is a plan view of a photo sensor according to a third embodiment.

FIG. 7 is a plan view of a photo sensor according to a fourth embodiment.

FIG. 8 is a plan view of a photo sensor according to a fifth embodiment.

FIG. 9 is a plan view of a photo sensor according to a sixth embodiment.

FIGS. 10A to G are cross sectional views illustrating a method of manufacturing a semiconductor device with the photo sensor of the first embodiment integrated with bipolar transistors.

FIGS. 11A and 11B are cross sectional views of conventional photo sensors.

CLAIMS

1. A semiconductor device comprising: an underlying substrate having at least a surface layer made of semiconductor of a first conductivity type; a first layer formed on or over said surface layer of said underlying substrate and made of semiconductor having a resistance higher than a resistance of the surface layer of said underlying substrate; a first impurity diffusion region formed in a partial surface region of said first layer and doped with impurities of a second conductivity type opposite to the first conductivity type, said first impurity diffusion region not reaching a surface of said underlying substrate; a second impurity diffusion region of the first conductivity type disposed in said first layer and spaced apart from said first impurity diffusion region by a certain distance in an in-plane direction, said second impurity diffusion region reaching the surface of said underlying substrate; and a first separation region disposed between said first and second impurity diffusion regions, wherein a trench is formed in said first layer, and wherein dielectric material is disposed at least in a partial internal region of the trench.

2. A semiconductor device according to claim 1, further comprising an antireflection film formed at least on a partial surface region of said first impurity diffusion region.

3. A semiconductor device according to claim 1, further comprising electrodes for applying a reverse bias voltage to said first and second impurity diffusion regions.

4. A semiconductor device according to claim 1, wherein said first layer comprises a first lower layer and a first upper layer formed on the first lower layer, the first lower layer being located from the first upper layer to the underlying substrate side and being made of semiconductor of the first conductivity type, and having an impurity concentration lower than an impurity concentration of the surface layer of said underlying substrate of the first conductivity type.

5. A semiconductor device according to claim 4, wherein said first separation region reaches a position deeper than a boundary between the first upper and lower layers.

6. A semiconductor device according to claim 4, wherein: said first separation region does not reach an interface between said first layer and said underlying substrate; and a high impurity concentration region of the first conductivity type having an impurity concentration higher than an impurity concentration of a region just under said first impurity diffusion region is fanned in said first layer on the bottom of said first separation region, said high impurity concentration region being disposed in the first lower layer and not reaching the first upper layer.

7. A semiconductor device according to claim 1, further comprising: a third impurity diffusion region disposed in said first layer adjacent to said first impurity diffusion region, spaced apart from said first and second impurity diffusion regions by a certain distance in the in-plane direction, and doped with impurities of the second conductivity type, said third impurity diffusion region not reaching the surface of said underlying substrate; and a second separation region disposed in said first layer between said first and third impurity diffusion regions, said second separation region electrically separating said first and third impurity diffusion regions, wherein said first separation region is disposed also between said second and third impurity diffusion regions.

8. A semiconductor device according to claim 7, wherein said second separation region comprises a region doped with impurities of the first conductivity type.

9. A semiconductor device according to claim 8, wherein said second separation region is in contact with said first separation region.

10. A semiconductor device according to claim 9, wherein a region in contact with the first separation region, of the second separation region, is doped with impurities of the first conductivity type in addition to impurity implantation for forming said second separation region.

11. A semiconductor device according to claim 8, wherein said second separation region reaches said second impurity diffusion region and said first separation region abuts on a side wall of said second separation region.

12. A semiconductor device according to claim 7, wherein said second separation region includes a trench formed in said first layer and dielectric material disposed at least in a partial internal region of the trench.

13. A semiconductor device according to claim 12, wherein the trench constituting said second separation region is branched from the trench constituting said first separation region.

14. A semiconductor device according to claim 7, wherein said first separation region is disposed continuously from a region between said first and second impurity diffusion regions to a region between said third and second impurity diffusion regions, and said second separation region abuts of a side wall of said first separation region.

15. A semiconductor device according to claim 1, wherein said first separation region comprises a plurality of divisions disposed in a direction in which said first and second impurity diffusion regions are separated, each of the divisions comprising a trench formed in said first layer and dielectric material disposed at least in a partial internal region of the trench.

16. A semiconductor device according to claim 1, wherein said first separation region is disposed spaced apart from said second impurity diffusion region.

17. A semiconductor device according to claim 1, further comprising a bipolar transistor formed in and on a surface layer of said first layer, said bipolar transistor comprising a collector region formed in said first layer, a base region disposed between the collector region and an upper surface of said first layer and contacting the collector region and the first layer, and an emitter region disposed on the base region and made of impurity doped polysilicon.

18. A semiconductor device comprising: an underlying substrate having at least a surface layer made of semiconductor of a first conductivity type; a first layer formed on said surface layer of said underlying substrate and made of semiconductor having a resistance higher than a resistance of the surface layer of said underlying substrate; a first impurity diffusion region formed in a partial surface region of said first layer and doped with impurities of a second conductivity type opposite to the first conductivity type, said first impurity diffusion region not reaching a surface of said underlying substrate; a second impurity diffusion region of the first conductivity type disposed in said first layer and spaced apart from said first impurity diffusion region by a certain distance in an in-plane direction, said second impurity diffusion region reaching the surface of said underlying substrate; a trench formed in said first layer, the trench surrounding a region in which said first and second impurity diffusion regions are disposed; and a dielectric material member disposed at least in a partial internal region of said trench.

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