Integrated circuit having conductive paths of different heights formed from the same layer structure and method for forming the same

ABSTRACT

An integrated circuit includes a substrate having a surface. A first conductive path is disposed on the substrate at a first level and has a first height. A second conductive path is also disposed on the substrate at the first level and has a second height that is significantly different than the first height. Where the integrated circuit is a memory circuit, the digit lines formed from a layer can have a smaller height than other signal lines that are formed from the same layer. Thus, the capacitive coupling between the digit lines can be reduced without degrading the current carrying capability of the other signal lines.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

CROSS-REFERENCE TO RELATED APPLICATION

This application is a divisional of pending U.S. patent application Ser. No. 08/928,556, filed Sep. 12, 1997 now abandoned.

DETAILED DESCRIPTION OF THE INVENTION

Referring to FIG. 1, an integrated circuit, such as a memory circuit, is formed from a semiconductor layer structure , which includes a substrate that is conventionally formed from a material such as silicon. The structure includes an insulator layer that is formed on the substrate at a first level, and a conductive layer structure having a thickness t1 that is formed on the layer at a second level. In one embodiment, the structure includes a single conductive layer that is disposed on the insulator layer . In another embodiment, the layer structure may also include a conventional barrier layer , which may be formed from titanium or titanium nitride and be between 100 and 1,000 Angstroms (Å) thick. For example, the insulator layer may be formed from silicon dioxide or another conventional dielectric, and the conductive layer may be formed from polysilicon, silicided polysilicon, a metal, such as aluminum that is deposited by conventional sputtering, or another conductive material. Additionally, it is understood that the layer structure may not have a uniform thickness over its area, in which case the thickness t1 is an average thickness. Furthermore, for clarity, only layers , and are shown, it being understood that other layers may be disposed between the substrate and the layer , or between the layers and .

Referring to FIG. 2, a first mask is conventionally formed over a first region of the structure where signal lines are to be formed. A region of the structure where the digit lines are to be formed is left exposed. Next, the thickness of the layer structure in the exposed region is conventionally reduced to a desired thickness t2. For example, the portion of the layer in the exposed region may be isotropically or anisotropically etched. Then, the mask is removed. Although shown formed as a single layer structure, in other embodiments of the invention the layer structure may comprise two portions that are separately formed in the regions and using conventional techniques and having the same thickness t1. Alternatively, the portion of the layer structure over the region may be formed having the thickness t2 to eliminate the thickness-reducing etching step.

In one embodiment shown in FIG. 3, an optional anti-reflective coating, i.e., cap layer , is then formed over the layer after the mask is removed. For example, the cap layer may include the same material as the barrier layer .

With further reference to FIG. 3, the portions of the conductive layer , the barrier , and the cap layer in the region have or substantially have a combined thickness t3, and the portions of the conductive layer , barrier layer and the cap layer in the region and the cap layer have a reduced thickness t4, which is significantly less than the thickness t3. In embodiments that do not include the layer , t3=t1 and t4=t2.

Referring to FIG. 4, signal lines having substantially the thickness t3, are formed by conventionally etching the portions of the layers , , and in the region , and digit lines having substantially the thickness t4 are formed by conventionally etching the portions of the layers , , and in the region . In one embodiment, the digit lines are approximately 4000 Å thick, and the signal lines are approximately 8000 Å thick.

Thus, lines having different thicknesses can be formed in the same level of a semiconductor structure such as the structure , and can also be formed from the same layer structure of material.

Furthermore, it is well known from capacitor theory that as the overlapping area of the capacitor plates decreases, the capacitance also decreases. Thus, in the described embodiment, the reduction in the thicknesses of the digit lines reduces the areas of the sides , and thus reduces the coupling capacitances between adjacent ones of the lines . In a dynamic random access memory (DRAM), this decrease in coupling capacitance increases the ratio between the cell capacitance and the coupling capacitance, thus making more charge available to charge the cell capacitance. Therefore, reducing the coupling capacitances often increases the reading and writing speeds of the memory cells coupled to the lines , and thus often reduces or eliminates reading and writing errors due to cross talk.

It is true that reducing the thickness of the digit lines increases their resistance. However, the reduction in coupling capacitance is significantly greater than the increase in resistance. Therefore, there is an overall increase in the reading and writing speeds as discussed above.

It is well known that as the thickness of a line is reduced, the line's current-carrying capacity is also reduced. In some embodiments of the invention, the signal lines may be power-supply, ground-return, or other lines that carry relatively large currents as compared to the currents carried by the digit lines . Thus, by allowing the signal lines to have relatively large thicknesses even when the thicknesses of other lines formed from the same layer structure are reduced, the current-carrying capacities of the lines are not degraded. Furthermore, in one embodiment of the invention, the memory array is formed in the region , and power-supply lines are formed in the region , which is peripheral to the memory array in the region . In another embodiment, the memory array includes both regions and .

FIGS. 5-7 show a second embodiment of a method for forming a memory circuit having digit lines that are reduced in height with respect to other signal lines that are formed from the same conductive layer structure. During the etch of the layer in the region as discussed above, it is sometimes difficult to etch the layer structure to a uniform thickness across the region . This difficulty may be caused by process characteristics, such as temperature and pressure, that vary at different points of the region .

Therefore, as discussed below, one major difference from the first embodiment is that the layer structure includes multiple conductive layers, one of which is an etch-stop layer.

Referring to FIG. 5, a conductive layer structure is formed on the insulator layer at a second level, and includes the optional barrier layer , a first conductive layer that is formed on the barrier layer in a first sublevel of the structure , a second conductive layer formed on the layer at a second sublevel, and the conductive layer , which, in this embodiment, is a third conductive layer formed on the layer at a third sublevel. The structure has a thickness of t5, which is the sum of the thicknesses of the layers , , , and . Furthermore, the layers , , and have a combined thickness t6, which is less than the thickness t5. Additionally, as discussed below, the layers and are formed from different materials. For example, the layer may include titanium nitride or a titanium-tungsten alloy, and the layers and may include aluminum disposed by a conventional sputter/deposition step.

Referring to FIG. 6, the first mask is formed over the region , and the exposed portion of the layer in the region is conventionally etched down to the layer , which acts as an etch-stop layer. That is, the etchant used to etch the layer etches the layer much faster than it etches the layer . Thus, the etch-stopping point can often be more reliably controlled than in the first embodiment described in conjunction with FIGS. 1-4. Next, the mask is then removed. Thus, the layer structure now has substantially the thickness t6 in the region , and has substantially the thickness t5 in the region .

Referring to FIG. 7, the digit lines are formed in the region from the layers , , and , and the signal lines are formed in the region from the layers , , , and . As in the first embodiment, the digit lines are of the significantly reduced thickness, here t6, as compared with the thickness of the signal lines , here t5. This reduces the coupling capacitances between adjacent digit lines .

In another embodiment of the invention, the layer is omitted such that the semiconductor structure includes only the layers , , and . In this embodiment, the layers and are formed to the desired thickness t6, and the digit lines are formed from two layers, the layers and , and not three layers as described in conjunction with FIGS. 5-7.

FIG. 8 is a block diagram of one embodiment of a memory circuit that can be formed according to the methods described above in conjunction with FIGS. 1-4 and FIGS. 5-7, respectively. The memory circuit includes memory banks and These memory banks each incorporate a memory array according to the invention. In one embodiment, the memory circuit is a synchronous DRAM (SDRAM), although it may be another type of memory in other embodiments.

The memory circuit includes an address register , which receives an address from an ADDRESS bus. A control logic circuit receives a clock (CLK) signal, receives clock enable (CKE), chip select ({overscore (CS)}), row address strobe ({overscore (RAS)}), column address strobe ({overscore (CAS)}), and write enable ({overscore (WE)}) signals from the COMMAND bus, and communicates with the other circuits of the memory device . A row-address multiplexer receives the address signal from the address register and provides the row address to the row-address latch-and-decode circuits and for the memory bank or the memory bank respectively. During read and write cycles, the row-address latch-and-decode circuits and activate the word lines of the addressed rows of memory cells in the memory banks and respectively. Read/write circuits and read data from the addressed memory cells in the memory banks and respectively, during a read cycle, and write data to the addressed memory cells during a write cycle. A column-address latch-and-decode circuit receives the address from the address register and provides the column address of the selected memory cells to the read/write circuits and For clarity, the address register , the row-address multiplexer , the row-address latch-and-decode circuits and and the column-address latch-and-decode circuit can be collectively referred to as an address decoder.

A data input/output (I/O) circuit includes a plurality of input buffers . During a write cycle, the buffers receive and store data from the DATA bus, and the read/write circuits and provide the stored data to the memory banks and respectively. The data I/O circuit also includes a plurality of output drivers . During a read cycle, the read/write circuits and provide data from the memory banks and respectively, to the drivers , which in turn provide this data to the DATA bus.

A refresh counter stores the address of the row of memory cells to be refreshed either during a conventional auto-refresh mode or self-refresh mode. After the row is refreshed, a refresh controller updates the address in the refresh counter , typically by either incrementing or decrementing the contents of the refresh counter by one. Although shown separately, the refresh controller may be part of the control logic in other embodiments of the memory device .

The memory device may also include an optional charge pump , which steps up the power-supply voltage VDD to a voltage VDDP. In one embodiment, the pump generates VDDP approximately 1-1.5 V higher than VDD. The memory circuit may also use VDDP to conventionally overdrive selected internal transistors.

FIG. 9 is a block diagram of an electronic system , such as a computer system, that incorporates the memory circuit of FIG. . The system also includes computer circuitry for performing computer functions, such as executing software to perform desired calculations and tasks. The circuitry typically includes a processor and the memory circuit , which is coupled to the processor . One or more input devices , such as a keyboard or a mouse, are coupled to the computer circuitry and allow an operator (not shown) to manually input data thereto. One or more output devices are coupled to the computer circuitry to provide to the operator data generated by the computer circuitry . Examples of such output devices include a printer and a video display unit. One or more data-storage devices are coupled to the computer circuitry to store data on or retrieve data from external storage media (not shown). Examples of the storage devices and the corresponding storage media include drives that accept hard and floppy disks, tape cassettes, and compact disk read-only memories (CD-ROMs). Typically, the computer circuitry includes address data and command buses and a clock line that are respectively coupled to the ADDRESS, DATA, and COMMAND buses, and the CLK line of the memory device .

From the foregoing it will be appreciated that, although specific embodiments of the invention have been described herein for purposes of illustration, various modifications may be made without deviating from the spirit and scope of the invention. For example, although the invention is described with respect to digit lines and signal lines in a memory circuit, other types of conductors, such as word lines or other circuit interconnections, can be formed in the same level or from the same layer structure and have different thicknesses. Accordingly, the invention is not limited except as by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-4 are cross-sectional views that show a method for forming a memory circuit according to a first embodiment of the invention.

FIG. 1 is a first cross-sectional view that shows a method for forming a memory circuit according to a first embodiment of the invention.

FIG. 2 is a second cross-sectional view that shows a method for forming a memory circuit according to a first embodiment of the invention.

FIG. 3 is a third cross-sectional view that shows a method for forming a memory circuit according to a first embodiment of the invention.

FIG. 4 is a fourth cross-sectional view that shows a method for forming a memory circuit according to a first embodiment of the invention.

FIGS. 5-7 are cross-sectional views that show a method for forming a memory circuit according to a second embodiment of the invention.

FIG. 5 is a first cross-sectional view that shows a method for forming a memory circuit according to a second embodiment of the invention.

FIG. 6 is a second cross-sectional view that shows a method for forming a memory circuit according to a second embodiment of the invention.

FIG. 7 is a third cross-sectional view that shows a method for forming a memory circuit according to a second embodiment of the invention.

FIG. 8 is a block diagram of a memory circuit that can be formed according to the methods described in conjunction with FIGS. 1-4 and FIGS. 5-7.

FIG. 9 is a block diagram of an electronic system that incorporates the memory circuit of FIG. .

CLAIMS

1. A method for forming a memory circuit, comprising: forming a structure on a substrate, the structure including a first conductive layer disposed on the substrate, a second conductive layer disposed on the first conductive layer, and a third conductive layer disposed on the second conductive layer; removing the third conductive layer from a first region of the structure while preserving the third conductive layer in a second region of the structure; forming digit lines from the first and second conductive layers in the first region of the structure in a directional normal to the substrate; and forming a high current line in a space parralled relationship with the digit lines, the high current line being formed from the first, second, and third conductive layers in the second region of the substrate.

2. The method of claim 1 wherein the removing comprises: masking the second region of the structure; and etching the first region of the structure with an etchant that etches the third layer significantly faster than the second layer.

3. The method of claim 1 wherein the high current lines comprise power supply lines.

4. The method of claim 1 wherein the high current lines comprise ground lines.

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