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A method of improving shallow trench isolation (STI) gap fill and moat nitride pull back is provided by after the steps of growing a pad oxide, depositing a nitride layer on the pad oxide and the steps of moat patterning, moat etching and moat clean, the steps of growing thermal oxide, deglazing a part of a part of the moat nitride; depositing a thin nitride liner, etching the nitride to form a thin side wall nitride in the STI trench; and performing an oxide Hydroflouric (HF) acid deglazing before STI liner oxidating and depositing oxide to fill the trench.
DETAILED DESCRIPTION OF THE INVENTION
This application claims priority under 35 USC § 119(e)(1) of provisional application No. 60/365,832 filed Mar. 21, 2002.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIGS. 1-7 are partial side elevation views in section illustrating a conventional shallow trench isolation process for providing isolation between active areas in a semiconductor device;
FIG. 8 is an STI trench post liner oxidation;
FIG. 9 is a moat corner with STI oxide recess;
FIG. 10 is an STI trench post side wall nitride liner formation; and
FIG. 11 is a flow chart of the process in accordance with a preferred embodiment of the present invention.
DESCRIPTION OF THE PREFERRED EMBODIMENT OF THE INVENTION
Before describing the preferred embodiment of the present invention a description of the following is the present process sequence for STI formation.
A. Grow a pad oxide on the face of silicon wafers. The pad oxide layer may be formed using any appropriate oxidation processes as are known such as a thermal oxidation growth or a deposition process. The pad oxide layer may function to relieve stress between the underlying silicon substrate and the overlying nitride layer to follow.
B. Deposit a nitride layer on top of the pad oxide. The nitride layer operates as a hard mask in subsequent isolation processing to protect the underlying active regions of the substrate. The nitride layer may be formed using any appropriate deposition techniques and materials such as Si3N4 deposited by low pressure chemical vapor deposition (LPCVD).
C. Pattern (resist coat, exposure and develop) the moat. A resist layer is formed over the nitride layer, and patterned to form a patterned mask exposing isolation regions of the substrate, while covering the active regions. The patterning of the resist mask may be done according to known photolithography methodologies such as by exposing select portions of the resist to a radiation source through a photomask, and removing either the exposed or the unexposed portions of the resist material so as to uncover a portion of the nitride layer in the isolation regions and to leave the active regions covered.
D. Etch the nitride, oxide and silicon to form the shallow trench. An isolation trench is dry etched using the patterned mask formed. The trench etch may be carried out using known trench etching techniques such as reactive ion etching (RIE). For example, a multi-step RIE etch process may be performed which removes material in the exposed isolation regions so as to etch through the nitride layer, the underlying pad oxide, and into the semiconductor substrate so as to form a trench having sidewalls, a bottom, and lower corners therebetween. For instance, a first dry etch may be employed to remove the nitride and oxide material in the isolation region so as to expose the silicon wafer surface. Thereafter, a second dry etch may be performed to remove the silicon surface area through the openings in the mask to form a trench therein.
E. Resist clean up.
F. Hydroflouric (HF) acid deglaze for STI oxide liner under cut.This is to clean the STI silicon surface prior to the oxide liner growth and also it deglazes a part of the pad oxide under the moat nitride for stress release.
G. Grow an oxide liner.
H. Deposit oxide to fill the STI trenches. The trench is filled with dielectric material such as SiO2 or other electrically isolating material so as to provide electrical isolation between active regions on either side of the isolation trench. The trench filling operation may comprise forming or depositing dielectric material over the device to cover the nitride layer in the active regions and to fill the trenches in the isolation regions thereof. The trench fill material may be deposited using any appropriate material.
I. CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is an stopping layer for CMP.
J. Moat nitride etch (Hot Phosphoric acid).
K. Grow dummy oxide, HF deglaze, grow high voltage (HV) gate, HF deglaze and grow low voltage (LV) gate oxide.
L. Deposit polysilicon and form the transistor gates.
The difficulties that might occur are:
a. At step G, the oxide liner is not grown uniformly around the STI trench due to the different silicon plane orientations where this in effect will cause problems at step H for the gap fill and it will cause a void in the STI fill as it is shown in FIG. .
b. At step K, all the oxide deglazes in the standard process, will also remove the STI oxide from top and from the sides. If some STI oxide is removed from the top, it will not cause any problems. But the STI oxide recess at the moat corners will cause problems for the transistors where, in effect, the sharp moat corners will cause the inverse narrow width effect. This is shown in FIG. .
In accordance with one embodiment of the present invention:
1) A method to reduce oxide growth on STI walls is provided by depositing and etching a nitride liner to create a thin side wall prior to the STI liner oxidation.
2) A method to make the moat nitride pull back process possible in the presence of the STI nitride liner process for STI stress reduction is provided by depositing and etching a nitride liner to create a thin side wall nitride prior to the STI gap fill.
The present invention teaches a preferred “process method” for the STI loop processes in order to obtain a much more process capability for the STI gap fill by suppressing the oxide growth rate on STI walls and also make the moat nitride pull back possible to solve the STI oxide recess problem at the moat corners. This preferred method can be used to solve the above two problems separately or both.
The combined process steps (illustrated in FIG. 11) to solve the nonuniformity of the STI oxide liner growth and moat nitride pull back are as follows:
1. Grow a pad oxide on the face of silicon wafers as discussed previously.
2. Deposit a nitride layer on top of the pad oxide as discussed previously.
3. Moat pattern, moat etch and moat etch clean are done per base line. This is steps C-E discussed above.
4. Grow 20-40 Angstroms of thermal oxide (For good silicon-oxide interface, also it prevents silicon loss or roughening of silicon surface during the hot phosphoric wet moat nitride pull back).
5. Use hot phosphoric acid to etch a part of the moat nitride. Therefore the moat nitride will be thinner on the top and also it will pull back laterally. This lateral removal of moat nitride will be filled with the STI gap fill later, where, in effect, prevents the STI oxide recess at the moat corners.
6 Deposit a very thin nitride liner (30-60 Angstroms).
7 Perform dry nitride etch to form side wall nitride in the STI trench as illustrated by in FIG. . Therefore the original moat nitride and the new STI side wall nitride are in effect separated where during the subsequent moat nitride wet etch the STI side wall nitride in the STI trench will not be affected by this wet etch.
8. Hydroflouric (HF) acid deglaze process (for under cut and moat pad oxide deglaze).
9. STI liner oxidation (This will grow oxide on the bottom of STI where nitride has been etched and also it will prevents too much oxide growth on the walls. Meanwhile amount of corner rounding stays the same as before. FIG. 10 depicts this process with thin nitride post nitride etch and STI liner oxidation. This side wall nitride can be left in the STI trench to reduce the stress in STI.)
The steps 10 through 14 following the STI oxide liner growth are then performed as discussed above.They are as follows:
10. Deposit oxide to fill the STI trenches.
11. CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP.
12. Moat nitride etch (Hot Phosphoric acid).
13. Grow dummy oxide, HF deglaze, grow HV gate, HF deglaze and grow LV gate oxide.
14. Deposit polysilicon and form the transistor gates.
Although the invention has been illustrated and described with respect to one or more implementations, equivalent alterations and modifications will occur to others skilled in the art upon the reading and understanding of this specification and the annexed drawings. In particular regard to the various functions performed by the above described components (assemblies, devices, circuits, systems, etc.), the terms (including a reference to a “means”) used to describe such components are intended to correspond, unless otherwise indicated, to any component which performs the specified function of the described component (e.g., that is functionally equivalent), even though not structurally equivalent to the disclosed structure which performs the function in the herein illustrated exemplary implementations of the invention. In addition, while a particular feature of the invention may have been disclosed with respect to only one of several implementations, such feature may be combined with one or more other features of the other implementations as may be desired and advantageous for any given or particular application. Furthermore, to the extent that the terms “including”, “includes”, “having’, “has”, “with”, or variants thereof are used in either the detailed description and the claims, such terms are intended to be inclusive in a manner similar to the term “comprising.”
1. A method of STI formation on a silicon wafer comprising the steps of: growing pad oxide on the face of the silicon wafer; deposit nitride layer on said pad oxide; moat patterning, moat etching and moat etch cleaning; growing thermal oxide; etching a part of the moat nitride layer using hot phosphoric acid; depositing a very thin nitride liner; dry plasma etching the thin nitride liner to form a thin side wall nitride in the STI trench separated from the moat nitride layer such that during subsequent moat nitride wet etch the side wall nitride in the STI trench will not be affected; performing Hydrofluoric (HF) acid deglaze process; and performing STI liner oxidation.
2. The method of claim 1 including the step of depositing oxide to fill the STI trenches.
3. The method of claim 2 including the steps of CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP; moat nitride etch; growing dummy oxide; HF deglazing, growing HV gate, HF deglaze and grow LV gate oxide; and depositing polysilicon and forming the transistor gates.
4. The method of claim 1 wherein the growing thermal oxide grows 20-40 Angstroms.
5. The method of claim 1 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms.
6. The method of STI formation on a silicon wafer comprising the steps of: growing pad oxide on the face of the silicon wafer; deposit nitride layer on said pad oxide; moat patterning, moat etching and moat etch cleaning; growing thermal oxide; etching a part of the moat nitride layer; depositing a very thin nitride liner; dry plasma etching the thin nitride liner to form a thin side wall nitride in the STI trench separated from the moat nitride layer such that during subsequent moat nitride wet etch the side wall nitride in the STI trench will not be affected; deglazing for under cut and moat pad oxide deglaze; and performing STI liner oxidation; depositing oxide to fill the STI trenches; CMP (Chemical Mechanical Polishing) of the STI oxide where the moat nitride is a stopping layer for CMP; and performing moat nitride wet etch.
7. The method of claim 6 wherein the growing thermal oxide grows 20-40 Angstroms.
8. The method of claim 6 wherein the step of depositing a very thin nitride liner is from 30-60 Angstroms.
9. The method of claim 6 further including the step of: growing dummy oxide; HF deglazing, growing HV gate, HF deglaze and grow LV gate oxide; and depositing polysilicon and forming the transistor gates.
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