Nonvolatile memory device including write protected region

ABSTRACT

A nonvolatile memory device including a write protected region, comprising a program command processor, a write protected region setting unit and a write controller. The program command processor outputs a program command signal by decoding an external signal. The write protected region setting unit stores a region address corresponding to an inputted address when the program command signal is activated, and outputs a write protect signal when the program command signal is inactivated. The write controller controls a cell corresponding to the region address not to perform a write mode when the write protect signal is activated.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a block diagram showing a ferroelectric memory device including a write protected region according to an example of the present invention.

FIG. 2 is a structural diagram showing a main bitline pull-up controller, a cell array block and a column selection controller of FIG. .

FIG. 3 is a structural diagram showing the main bitline pull-up controller of FIG. .

FIG. 4 is a structural diagram showing a main bitline load controller of FIG. .

FIG. 5 is a structural diagram showing the column selection controller of FIG. .

FIG. 6 is a structural diagram showing a sub cell block of FIG. .

FIG. 7 is a structural diagram showing a program command processor according to the present invention.

FIG. 8 is a diagram showing the operation of the program command processor of FIG. .

FIG. 9 is a structural diagram showing a D flip-flop used in FIG. .

FIG. 10 is a structural diagram showing a register included in the memory device according to the present invention.

FIG. 11 is a timing diagram showing a write mode of the register of FIG. .

FIG. 12 is a timing diagram showing a read mode of the register of FIG. .

FIG. 13 is a circuit diagram showing a circuit for generating register control signals ENW and CPL of FIG. .

FIG. 14 is a block diagram showing a region address buffer unit included in the memory device according to the present invention.

FIG. 15 is a diagram showing a relation between an address of a write protected region and an address inputted to the memory device.

FIGS. 16and are structural diagrams showing a write protected region setting unit of FIG. .

FIGS. 17through are structural diagrams showing a write controller of FIG. .

DETAILED DESCRIPTION OF THE PREFERRED EMBODIEMTNS

The present invention will be described in more detail with reference to the accompanying drawings.

FIG. 1 is a block diagram showing a ferroelectric memory device including a write protected region according to an example of the present invention.

The nonvolatile memory device of the present invention comprises a cell array block , a main bitline pull-up controller , a column selection controller , a sense amplifier array , a switch controller and an I/O buffer . The main bitline pull-up controller pulls up a main bitline included in the cell array block to a positive voltage. The column selection controller connects the main bitline to a data bus unit . The sense amplifier array is connected to the data bus unit . The switch controller controls the sense amplifier array . The I/O buffer exchanges data with the sense amplifier array .

The nonvolatile memory device of the present invention also comprises a write controller , a write protected region setting unit , and a program command processor for performing a write protected operation.

The program command processor decodes a write protection command. The write protected region setting unit is controlled by an address inputted from an address buffer and an output signal from the program command processor to set up a write protected region. The write controller controls read or write operations in response to a write protect signal provided from a /WP buffer , a write enable signal provided from a /WE buffer , and an output signal from the write protection region setting unit .

FIG. 2 is a structural diagram showing a main bitline pull-up controller , a cell array block and a column selection controller of FIG. . The cell array block includes a plurality of main bitline load controllers and a plurality of sub cell blocks . When two or more main bitline load controllers are connected to one main bitline, the same number of sub cell blocks are assigned to a main bitline load controller and the main bitline load controllers are evenly placed apart from each other. All or some of the cell array blocks can be designated as protected regions (). A plurality of sub cell blocks ill may be included in a protected region . The sub cell blocks included in the same protected region operate in the same mode.

FIG. 3 is a structural diagram showing the main bitline pull-up controller of FIG. . The main bitline pull-up controller comprises a PMOS transistor having a gate to receive a control signal MBPUC, a source connected to a power source VPP(VCC), and a drain connected to a main bitline MBL.

The main bitline pull-up controller pulls up the main bitline MBL to a voltage VPP(VCC) in a precharge operation.

FIG. 4 is a structural diagram showing the main bitline load controller of FIG. . The main bitline load controller comprises a PMOS transistor having a gate to receive a control signal MBLC, a source connected to the power source VPP(VCC), and a drain connected to the main bitline MBL.

The main bitline load controller as a resistive device connected between the power source VPP(VCC) and the main bitline MBL determines a potential of the main bitline according to the amount of current flowing through the main bitline load controller in a data sensing operation.

The main bitline MBL is connected to one or more main bitline load controllers . When two or more main bitline load controllers are connected to the main bitline MBL, the main bitline load controllers are evenly placed apart from each other.

FIG. 5 is a structural diagram showing the column selection controller of FIG. . The column selection controller is a switch for connecting the main bitline MBL and the data bus. Its on/off operations are controlled by control signals CSN and CSP.

FIG. 6 is a structural diagram showing the sub cell block of FIG. . The sub cell block comprises a sub bitline SBL, and NMOS transistors N, N, N, N and N. The sub bitline SBL are connected in common to a plurality of unit cells, each of which is connected to a wordline WL and a plateline PL. The NMOS transistor N for regulating a current has a gate connected to a first terminal of the sub bitline SBL, and a drain connected to the main bitline MBL. The NMOS transistor N has a gate connected to a control signal MBSW, a drain connected to a source of the NMOS transistor N and a source connected to ground. The NMOS transistor N has a gate connected to a control signal SBPD, a drain connected to a second terminal of the sub bitline SBL and a source connected to ground. The NMOS transistor N has a gate connected to a control signal SBSW, a source connected to the second terminal of the sub bitline SBL and a drain connected to a control signal SBPU. The NMOS transistor N has a gate connected to a control signal SBSW, a drain connected to the main bitline MBL and a source connected to the second terminal of the sub bitline SBL.

When a unit cell is to be accessed, only the sub bitline connecting the unit cell is connected to the main bitline. Here, the sub bitline SBL is connected to the main bitline MBL via the NMOS transistor N. Accordingly, memory read/write operations can be performed even with a smaller amount of load corresponding to one sub bitline rather than a larger amount of load corresponding to the whole bitline.

The sub bitline SBL is grounded when the control signal SBPD is activated. The control signal SBPU regulates a voltage to be provided to the sub bitline SBL. The control signal SBSW regulates the flow of a signal between the sub bitline SBL and the main bitline MBL. The control signal SBSW regulates the flow of a signal between the control signal SBPU and the sub bitline SBL.

The sub bitline SBL connected to a gate of the NMOS transistor N regulates a sensing voltage of the main bitline. The main bitline MBL is connected to the power source VPP(VCC) via the main bitline load controller . When a control signal MBSW becomes at a high level, current flows from the power source VPP(VCC), through the main bitline load controller , the main bitline MBL and the NMOS transistors N and N, to ground. Here, the amount of the current is determined by a voltage of the sub bitline SBL connected to the gate of the NMOS transistor N. If data of a cell is “1”, the amount of the current becomes larger, thereby decreasing the voltage of the main bitline MBL. If data of a cell is “0”, the amount of the current becomes smaller, thereby increasing the voltage of the main bitline MBL. Here, the cell data can be detected by comparing the voltage of the main bitline MBL with a reference voltage. Detecting the cell data is performed in the sense amplifier array .

FIG. 7 is a structural diagram showing a program command processor included in the memory device according to the present invention. FIG. 8 is a timing diagram showing the operation of the program command processor according to the present invention. Referring to FIG. 8, the program command processor of FIG. 7 is explained. All D flip-flops of FIG. 7 are supposed to be synchronized at a falling edge of a clock signal.

If a write enable signal WEB and a chip enable signal CEB are activated to a low level, a clock signal generated by toggling an output enable signal OEB is provided to a clock input terminal. Since there are N D flip-flops connected serially, if the output enable signal OEB toggles N-times, a high level output from a NOR gate is propagated to an output signal WP_CMD of the Nth flip-flop. However, when the output signal WP_CMD is activated, if the output enable signal OEB becomes at the high level, all D flip-flops are reset. As a result, the output signal WP_CMD becomes at the low level. The output signal WP_CMD is activated at a Nth falling edge of the output enable signal OEB, and inactivated at the (N+1)th rising edge of the output enable signal OEB.

FIG. 9 is a structural diagram showing the D flip-flop used in FIG. . In general, a D flip-flop is a circuit for sampling and outputting a signal provided to an input terminal at a rising or falling edge of a clock. The circuit of FIG. 9 samples an input signal d at a falling edge of the clock CP. When the clock CP becomes “high”, a master unit turns on the gate S, and stores the input signal d in a latch. Here, since the gate S of a slave unit is turned off, the input signal d is not transmitted into a latch of the slave unit . If the clock CP becomes “low”, the gate S of the master unit is closed, and the gate S of the slave unit is opened. As a result, data stored in the latch of the master unit is stored in the latch of the slave unit , and the signal stored in the latch of the slave unit is continuously outputted until the next falling edge of the clock CP.

FIG. 10 is a structural diagram showing a register included in the memory device according to the present invention. The register comprises a first amplifier , an input unit , a storage unit and a second amplifier .

The first amplifier comprises PMOS transistors P, P and P. The PMOS transistor P has a gate to receive a first control signal ENP, and a source connected to a positive power source. The PMOS transistor P has a gate connected to a first node, a source connected to a drain of the PMOS transistor P, and a drain connected to a second node. The PMOS transistor P has a gate connected to the second node, a source connected to the drain of the PMOS transistor P, and a drain connected to the first node.

The second amplifier comprises NMOS transistors N, N and N. The NMOS transistor N has a gate connected to a first node, and a drain connected to a second node. The NMOS transistor N has a gate connected to the second node, and a drain connected to the first node. The NMOS transistor N has a gate to receive a second control signal ENN, a drain connected to a source of the NMOS transistor N and a source of the NMOS transistor N, and a source connected to ground.

The input unit comprises NMOS transistors N and N. The NMOS transistor N has a gate to receive a third control signal ENW, a source to receive a data signal RESET(AnB), and a drain connected to the first node. The NMOS transistor N has a gate to receive the third control signal ENW, a source to receive a data signal SET(An), and a drain connected to the second node.

The storage unit comprises ferroelectric capacitors FC, FC, FC and FC. The ferroelectric capacitor FC is connected between a fourth control signal CPL and the first node. The ferroelectric capacitor FC is connected between a fourth control signal CPL and the second node. The ferroelectric capacitor FC is connected between the first node and ground. The ferroelectric capacitor FC is connected between the second node and ground.

When the control signal ENP is “low” and the control signal ENN is “high”, the first amplifier and the second amplifier fix a node having a higher voltage between the first node and the second node at VCC and a node having a lower voltage at VSS. When the control signal ENP is “high” and the control signal ENN is “low”, the register is intercepted from the power source.

When the control signal ENW is “high”, the input unit provides data signals SET and RESET, respectively, to the second node and the first node. When the control signal ENW is “low”, the first node and the second node are intercepted from the data signals SET and RESET.

The storage unit stores data signals provided to the first node and the second node in the ferroelectric capacitors FC, FC, FC and FC by regulating the control signal CPL.

An output signal SPB_EN is outputted from the first node, and an output signal SP_EN is outputted from the second node.

FIG. 11 is a timing diagram showing a write mode of the register of FIG. . If the program command signal WP_CMD is activated, the program command processor of FIG. 4 is inactivated until the write process of the register is finished.

Referring to FIG. 11, the program command signal WP_CMD is activated in a cycle t, and a data signal DQ_n provided from the data I/O pad is transited from the high level to the low level. As a result, the control signal ENW is activated, and the data signals SET and RESET are provided, respectively, to the second node and the first node. If the signal CPL becomes at the high level, signals are stored in the ferroelectric capacitors FC through FC depending on the voltages of the first node and the second node. For example, when the first node is “low”, and the second node is “high”, charges are stored in the ferroelectric capacitors FC and FC.

In a cycle t, if the control signal ENW is “low”, the data signals SET and RESET are separated from the first node and the second node. The voltages of the first node and the second node are amplified and maintained by the first amplifier and the second amplifier . If the control signal CPL becomes “low”, charges are re-distributed between the ferroelectric capacitors FC and FC, and between the ferroelectric capacitors FC and FC. Here, the voltages of the first node and the second node vary with the re-distribution of the charges. The voltage of the second node becomes higher than that of the first node. The ferroelectric capacitors FC through FC maintain the stored charges even when the power source is turned off. In a cycle t, if the signals DQ_n becomes “high”, the program mode is finished. The signal DQ_n is used to generate a pulse signal (refer to FIG. ).

FIG. 12 is a timing diagram showing a read mode of the register of FIG. .

In the cycle t, if the power source reaches a stable level, a power-up detection signal PUP becomes activated. If the control signal CPL is transited to a “high” level using the signal PUP, voltage difference between the first node and the second node is generated by the charges stored in the ferroelectric capacitors FC to FC of FIG. .

In a cycle t, if the sufficient voltage difference is generated, the control signals ENN and ENP are activated, respectively, to a “high” level and to a “low” level. As a result, the data of the first node and the second node are amplified.

After the amplification of the data is completed, the control signal CPL is transited to a “low” level in the cycle t. As a result, the destroyed data are restored in the ferroelectric capacitors FC to FC. Here, the control signal ENW is inactivated to a “low” level, and the data signals SET and RESET are not provided to the second node and the first node.

FIG. 13 is a circuit diagram showing a circuit for generating register control signals ENW and CPL of FIG. . The control signal PUP is to restore data stored in the register after the initial reset. After the program command signal WP_CMD is activated, if the signal DQ_n is transited from a “high” level to a “low” level, the control signals ENW and CPL having a pulse whose width corresponds to the delay time of the delay circuit are generated (see FIG. ).

FIG. 14 is a block diagram showing a region address buffer unit included in the memory device according to the present invention. If a memory address is inputted, the region address buffer outputs region addresses SAn and SAn_B.

FIG. 15 is a diagram showing the relation between a memory address A and a region address SA. In a preferred embodiment of the present invention, one region address is assigned to every 2k memory addresses. The relation between the memory address and the region address may be freely varied according to preferred embodiments.

FIG. 16shows a structure of the write protected region setting unit of FIG. . The write protected region setting unit includes a master register REG_Master, and a plurality of registers REG_˜REGn. The output signals SP_EN and SPB_EN of the register REG_ are AND-operated with the region addresses SA and SA_B respectively. Two signals obtained from the AND operation are OR-operated. The rest registers REG_˜REG_n are configured to have the same operation processes. As a result, (n+1) OR operation results are obtained. A write protect signal WP_EN is obtained by ANDing the (n+1) OR operation results with an output signal SPM_EN from the master register REG_Master.

The write protected region setting unit activates a protection function only when the output signal SPM_EN of the master register REG_Master becomes “high”. If the signal SPM_EN becomes “low”, the protection function is not activated. In this example, an address of a region to be protected is programmed using a plurality of registers REG_, . . . , REG_n corresponding to a region address formed of (n+1) bits. If a predetermined region address SA is inputted, each bit SA0, . . . , SAn (SAn—B: a signal having an opposite level to SAn) is compared with the output signals SP_EN (SPB_EN: a signal having an opposite level to SP_EN) from registers REG_, . . . , REG_n corresponding to each bit.

For example, an address of a region to be protected is “101”, the output signal SP_EN of the register REG_ is set to be “high”, the output signal SP_EN of the register REG_ to be “low”, and the output signal SP_EN of the register REG_ to be “high”. As a result, when the region address “101” is inputted, output signals of all OR gates become “high”. Here, if the output signal SPM_EN of the master register REG_Master is “high”, the write protect signal WP_EN is activated to a “high” level. Since the registers REG_˜REG_n can be freely programmed, a protection function may be freely set for all protected regions.

FIG. 16shows another example of the write protected region setting unit of FIG. . In this example, registers REG_EXT˜REG_EXTn are added to the example of FIG. 16. A signal outputted from the register REG_EXT is AND-operated with an external control signal WP_EXT. The AND operation result is OR-operated with two signals obtained by ANDing the output signals SP_EN and SPB_EN of the register REG_ with the region address signals SA and SA_B. The example of FIG. 16has the same structure with that of FIG. 16

In the example of FIG. 16, the same operation is performed as described in FIG. 16. However, the added registers REG_EXT˜REG_EXTn perform the following operations. If a value of the register REG_EXTn is set as “1”, while the external control signal WP_EXT is “high”, only the rest region address bits SAn−1, . . . , SA0 are compared to determine activation of the signal WP_EN regardless of the value of SAn as “1” or “0”.

For example, a region address stored in the registers REG_˜REG_ is supposed to be “1111”. When the rest address bits are compared except a second bit, “0010” is stored in the register REG_EXT˜REG_EXT, and the external control signal WP_EXT is set “high”. As a result, the signal WP_EN can be activated to a “high” level when the inputted region address SA is “11×1”. When the rest address bits are compared except second and third bits, “0110” is stored in the register REG_EXT˜REG_EXT, and the external control signal WP_EXT is set “high”. As a result, when the inputted region address SA is “1xx1”, the signal WP_EN is activated to a “high” level.

FIG. 17is a structural diagram showing the write controller of FIG. . The output signal WP_EN of the write protected region setting unit of FIG. 16is OR-operated with an output signal WEB_EN of the write enable buffer (/WE buffer). The write controller is controlled by the result of OR operation. When the output signal WP_EN of the write protected region setting unit is “high”, the write controller starts a read mode regardless of the write enable signal WEB_EN. When the signal WP_EN is “low”, the write controller starts a write mode by the write enable signal WEB_EN.

FIG. 17is a structural diagram showing the write controller of FIG. 1 which includes the write protected /WP buffer, where an output signal of the /WP buffer is provided as the control signal WP_EXT of the write protected region setting unit of FIG. 16. The other structure is the same as that of FIG. 17

FIG. 17is a structural diagram showing the write controller of FIG. 1 which includes the write protected /WP buffer as shown in FIG. 17, where an output signal of the /WP buffer is provided as the control signal WP_EXT, and the write protected region setting unit is the same as that of FIG. 16. The write controller is controlled by a signal obtained by ORing the control signal WP_EXT, the output signal WP_EN of the write protected region setting unit , and the write enable signal WEB_EN. As a result, when the external control signal WP_EXT is activated, the write controller starts a read mode regardless of the output signal WP_EN of the write protected region setting unit and the write enable signal WEB_EN.

As discussed earlier, a nonvolatile memory device of the present invention includes a write protect function which can prevent data loss resulting from an undesired operation in a predetermined memory cell region.

CLAIMS

1. A nonvolatile memory device including a write protected region, comprising: a program command processor for outputting a program command signal by decoding an external signal; a write protected region setting unit for storing a region address corresponding to an inputted address when the program command signal is activated, and for outputting a write protect signal when the program command signal is inactivated; and a write controller for controlling a write operation not to be performed on a cell corresponding to the region address when the write protect signal is activated.

2. The device according to claim 1, wherein the program command signal is activated if an output enable signal toggles a predetermined number of times when a chip selection signal and a write enable signal are activated.

3. The device according to claim 2, wherein the program command signal is inactivated after the program command signal has been activated for the predetermined number of times.

4. The device according to claim 1, wherein the register comprises: a first amplifier for amplifying and fixing a voltage at a node having a higher potential, of a first node and a second node, into a predetermined positive voltage in response to a first control signal; a second amplifier for amplifying and fixing a voltage at a node having a lower potential, of the first node and the second node, into a ground voltage in response to a second control signal; an input unit for providing a data signal to the first node and the second node in response to a third control signal; and a storage unit for storing the signal provided to the first node and the second node in response to a fourth signal, where the stored signal is maintained when a power source is off, wherein voltages of the first node and the second node are externally outputted.

5. The device according to claim 4, wherein the first amplifier comprises: a first PMOS transistor having a gate to receive the first control signal, and a source connected to a positive power source; a second PMOS transistor having a gate connected to the first node, a source connected to a drain of the first PMOS transistor, and a drain connected to the second node; and a third PMOS transistor having a gate connected to the second node, a source connected to the drain of the first PMOS transistor, and a drain connected to the first node.

6. The device according to claim 4, wherein the second amplifier comprises: a first NMOS transistor having a gate connected to the first node, and a drain connected to the second node; a second NMOS transistor having a gate connected to the second node, and a drain connected to the first node; and a third NMOS transistor having a gate to receive the second control signal, a drain connected to a source of the first NMOS transistor and a source of the second transistor, and a source connected to a ground.

7. The device according to claim 4, wherein the input unit comprises: a first NMOS transistor having a gate to receive the third control signal, a source to receive a first data signal, and a drain connected to the first node; and a second NMOS transistor having a gate to receive the third control signal, a source to receive a second data signal, and a drain connected to the second node.

8. The device according to claim 4, wherein the storage unit comprises: a first ferroelectric capacitor connected between the fourth control signal and the first node; a second ferroelectric capacitor connected between the fourth control signal and the second node; a third ferroelectric capacitor connected between the first node and a ground; and a fourth ferroelectric capacitor connected between the second node and a ground.

9. The device according to claim 1, wherein the write protect region setting unit comprises: a register array for storing the region address; and a comparator for comparing a region address corresponding to the inputted address with an address stored in the register array, and outputting the write protect signal.

10. The device according to claim 9, wherein the write protected region setting unit further comprises a second register array having the same number of the register array, wherein the comparator compares the rest region address bits with the address bits stored in the register array except region address bits corresponding to activated bits stored in the second register array while an external control signal is activated, and outputs the write protect signal.

11. The device according to claim 9, wherein the write protected region setting unit further comprises a master register, and the write protect signal is not activated when a signal stored in the master register is not activated.

12. The device according to claim 10, wherein the write protected region setting unit further comprises a master register, and the write protect signal is not activated when a signal stored in the master register is not activated.

13. The device according to claim 1, wherein the write controller controls a write mode not to be performed on a memory region corresponding to the region address when the write protect signal or the external control signal is activated.

14. A nonvolatile memory device including a write protected region, comprising: a first register array including a pluarlity of registers where a region address is stored; a second register array including a plurality of the first register array corresponding to the plurality of registers; a master register for controlling activation; and a comparator for comparing a region address stored in the first register array with an externally inputted region address except those address bits corresponding to activated registers of the second register array, in response to an output value of the master register, and then outputting a comparison result.

15. A nonvolatile memory device including a write protected region, comprising: an internal protection signal controller for receiving an externally inputted address and an address of a predetermined protected region, and outputting an internal protection signal; an external protection signal controller for outputting an external protection signal in response to an external control signal; a write protect controller for receiving the internal protection signal and the external protection signal, and outputting a write protect signal; and a write controller for controlling read/write operations of the memory device in response to the write protect signal and a write enable signal.

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