Amplifier gain boost circuitry and method

ABSTRACT

A gain boost circuit is provided in a differential amplifier including differentially connected first and second input transistors the drains of which are coupled to sources of first and second cascode transistors. A third cascode transistor has a source coupled to a drain of the first cascode transistor and a drain coupled to a bias current source. A gain boost amplifier has an output coupled to the gate of the third cascode transistor, a first input coupled to the drain of the first cascode transistor, and a second input coupled to the drain of the second cascode transistor.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Referring to first to FIG. 3, differential amplifier input stage A includes P-type input transistors and having their sources connected by conductor to one terminal of constant current source , the other terminal of which is connected to V+. The drain of transistor is connected by conductor to the drain of N-channel load transistor and the (+) input of a gain boost amplifier . The drain of transistor is connected by conductor to the (−) input of gain boost amplifier and to the drain of N-channel load transistor . The output of gain boost amplifier is connected by conductor to the gates of transistors and , the sources of which are connected to V−. Conductor typically applies the single-ended output of differential amplifier input stage A to a suitable output stage (not shown). A voltage-input implementation of gain boost amplifier is shown in FIG. 4A, and a current-input implementation of gain boost amplifier is shown in FIG. B. The signal path from VIN+ and VIN− to VOUT in differential input stage A passes through input transistors and , gain boost amplifier , and the gate and drain of load transistor . Thus, gain boost amplifier is in the signal path of differential input stage A. The voltage gain of differential input stage A is equal to the transconductance of the pair of input transistors and multiplied by the parallel combination of equivalent impedance at the output of current mirror , and the impedance at the drain of transistor . Gain boost amplifier ensures that the output impedance of the current mirror , is very high, because the voltages of conductors and are forced to be nearly equal. Consequently, assuming that the load impedance connected to conductor is high, the utilization of gain boost circuit within differential input stage A as shown provides increased voltage gain.

In FIG. 4A, an operational amplifier A in includes differential amplifier input stage B with its single-ended output connected to the input of output stage . A voltage-input implementation of gain boost amplifier in differential amplifier input stage B is designated by reference numeral A, and includes differentially coupled P-channel input transistors and having their sources coupled by tail current source to V+ and their gates connected to conductors and , respectively. A suitable output stage has an input connected to conductor and produces VOUT. (The well-known output stage shown in above-mentioned U.S. Pat. No. 6,150,883 and also shown in FIG. 6 herein can be used as output stage .) N-channel transistors and constitute a conventional current mirror load circuit. The drain of transistor is connected to the drain and gate of load transistor and the gate of transistor , and the drain of transistor is connected by conductor to the gates of load transistors and and the drain of transistor . The sources of current mirror load circuit transistors and are connected to V−.

In FIG. 4B, a current-input implementation of gain boost amplifier in FIG. 3 is designated by reference numeral B, and includes differentially connected P-channel input transistors and having their sources connected to conductors and , respectively. The gate of transistor is connected by conductor to the gate and drain of transistor and to a current source load circuit . The drain of transistor is connected by conductor to the gate of load transistors and , and to one terminal of current source load circuit . The other terminals of current source load circuits and are connected to V−. The operational amplifier obtained by combining differential amplifier input stage C and output stage is designated by reference numeral B. The differential amplifier input stage circuits of FIGS. 3, A and B do not include folded-cascode circuitry, so single-supply operation is not practical. However, these circuits consume less current than differential amplifier input stage circuits including folded-cascode circuitry, and can be used as internal amplifiers within other amplifier circuitry. Also, the differential amplifier input stage circuits of FIGS. 3, and B provide more gain than prior art circuits of FIGS. 1A, B and .

Referring to FIG. 5A, an operational amplifier C includes a CMOS differential amplifier input stage D and an output stage . The CMOS differential amplifier input stage D includes P-channel input transistors and coupled to folded cascode circuitry and gain boost circuitry, and applies a single-ended output on conductor to an input of output stage to produce VOUT in response to VIN+ and VIN−, which are applied to the gates of transistors and , respectively. Note that if output stage is an inverting output stage (as shown in FIG. 6) then VIN+ and VIN− are applied to the gates of input transistors and , respectively, as shown. However, if the output stage is a non-inverting stage, then the coupling of VIN+ and VIN− to input transistors and shown in FIG. 5A should be reversed.) The drains of input transistors and are connected by conductors and to the drains of N-channel load transistors and , respectively, as in Prior Art FIG. . (Note that load transistors and are generally considered to be part of the folded cascode circuit.) N-channel cascode transistors and have their sources connected to conductors and , respectively and their gates connected to VBIAS. The drain of cascode transistor is connected by conductor to the (+) input of gain boost amplifier , to the input of output stage , and to one terminal of current source , the other terminal of which is connected to V+.

The output of gain boost amplifier is connected by conductor to the gate of a third N-channel cascode transistor , the source of which is connected by conductor to the drain of cascode transistor and to the (−) input of gain boost amplifier . The drain of cascode transistor is connected by conductor to one terminal of a level shift circuit and to one terminal of a current source circuit , the other terminal of which is connected to V+. The other terminal level shift circuit is connected by conductor to the gates of load transistors and , the sources of which are connected to V−. Level shift circuit provides “head room” for the third cascode transistor , so that its drain-to-source voltage is greater than 0 while an appropriate voltage is being applied to the gates of load transistors and . (Note that the amount of headroom trades-off directly with the minimum required operating voltage, where the operating voltage is defined here as VOP≡(V+)−(V−). (More headroom offers a wider voltage range on conductor but requires higher VOP. Less headroom allows lower VOP, critical for low supply voltage applications, at the expense of less voltage range on conductor , i.e., output stage drive.) The signal path from VIN+ and VIN− to VOUT in differential input stage D passes through the gates and drains of input transistors and and through cascode transistors and , so gain boost amplifier is not in the signal path. The amplifier of FIG. 5A has the advantages of increased gain and improved stability over the prior art circuits. When the voltage of conductor increases, gain boost amplifier operates to increase the gate voltage of transistor to keep the voltage on conductor equal to the voltage on conductor . That means the output current of the folded cascode circuitry through the drain of cascode transistor is determined by current source and the difference between the input currents, i.e., the drain currents of transistors and , as long as the combination of transistor and gain boost amplifier has sufficiently high gain, so the output impedance of folded cascode circuitry remains very high. The circuit of FIG. 5A operates to make the drain terminals of both of the cascode transistors and in the folded-cascode stage track in the presence of changing output voltage on conductor . The voltage on conductor is forced to track the voltage on conductor via the control loop including gain boost amplifier and cascode transistor . Hence, the drain-to-source-voltages of cascode transistors and track as the output voltage on conductor is driven. In contrast, this concept is not present in prior art. For example, in FIG. 1B, the voltage on conductor is fixed while the voltage on conductor is connected to the output stage and therefore is variable. Consequently, the drain-to-source-voltages of transistors and differ as the output voltage is driven.

Hence, a current-mirror-like arrangement that provides an extremely high output impedance is at the core of the present invention. The application of this current-mirror-like arrangement in a folded-cascode amplifier stage provides extremely high gain and can be made to operate at high speed by using of minimum channel length transistors and , which are acceptable because of the increased gain achieved by use of the boost circuit as shown. To go further, the use of an extremely high gain folded-cascode amplifier stage in a two stage amplifier topology provides a compact, i.e. low cost, high speed amplifier capable of maintaining high gain for a very wide range of resistive loads.

FIG. 5B shows operational amplifier C of FIG. 5A with a voltage-input implementation of gain boost amplifier including N-channel input transistors and with their sources coupled to V− by a tail current source and their drains connected to a P-channel current mirror load circuit including transistors and . The drain of transistor is connected by conductor to the gate of third cascode transistor and to the drain of load transistor . The gate of transistor is connected to conductor . The drain of transistor is connected to the gate and drain of load transistor and to the gate of load transistor . The gate of transistor is connected to the output conductor of differential amplifier stage D. Level shift circuit of FIG. 5A is implemented in FIG. 5B by means of source follower transistor A and diode-connected transistor B and a bias current source coupled series between V+ and V− as shown. This configuration requires a minimum operating voltage, VOP(MIN)=VGS(8,9)+VGS(31B)+VGS(31A)+Vdsat(13), where Vdsat(13) is the saturation voltage of the real current source symbolized by . Alternatively, if transistors and are sized such that their VGS(8,9)>(VDsat(8)+VDsat(10)+VDsat(33)+ΔV15), where VGS(8,9) is the voltage at the gates of transistors and and ΔV15, is a small but acceptable range of voltage swing on conductor , then the level shift circuit block in FIG. 5A can be realized by a wire, i.e. shorting conductors and and VOP(MIN) can be reduced. Note that while a current-input implementation of gain boost amplifier of FIG. 5A could be provided, there is no need to do so because the differential input stage D shown therein is very stable.

FIG. 5C shows an operational amplifier D including a differential folded cascode input stage E driving output stage . Gain boost amplifier has a (+) input connected to the drain of cascode transistor and one terminal of current source circuit , the other terminal which is connected to V+. The (−) input of gain boost amplifier is connected by conductor to one terminal of current source and to the drain of cascode transistor . The output of gain boost amplifier is connected to the gates of N-channel load transistors and . The signal path from VIN+ and VIN− to VOUT in differential input stage E passes through the gates and drains of input transistors and and the source and drain of cascode transistor to conductor , and therefore does not pass through gain boost amplifier . The differential input stage E of FIG. 5C does not require use of the level shift or of FIG. A and therefore can be used with lower amplitude supply voltages than the circuit of FIG. A. The differential input stage C of FIG. 5C also has substantially greater gain then the prior art circuits shown in FIG. .

FIG. 5D shows operational amplifier D of FIG. 5C with a current-input implementation of gain boost amplifier including differentially connected P-channel input transistors and having their sources connected conductor and , respectively. The gate of transistor is connected to the gate and drain of transistor . The drain of transistor and are coupled to V− by current load circuits and , respectively. The drain of transistor is connected to the gates of load transistors and . (Note that use of a current-input rather than a voltage-input implementation of gain boost amplifier substantially improves the circuit stability, but at the cost of an increased amount of noise.)

FIG. 5E shows an operational amplifier E including a current-input implementation of gain boost circuit that is similar to the circuit in Prior Art FIG. 2 except that the output of gain boost amplifier is connected to the gate of cascode transistor rather than cascode transistor . However, in the circuit of Prior Art FIG. 2 the signal path includes the gain boost amplifier. In contrast, in the circuit of FIG. 5E the signal path from VIN+ and VIN− to VOUT in the differential input stage passes through the gates and drains of input transistors and and the source and drain of cascode transistor to conductor , and therefore does not pass through gain boost amplifier . Consequently, the principles of operation of the circuit of FIG. 5E are very different from the circuit of Prior Art FIG. .

FIG. 6 is a schematic diagram showing a typical implementation of the CMOS differential amplifier stage of FIG. 5A that is included in a rail-to-rail operational amplifier F. In FIG. 6, the differential input stage D shown in FIG. 5A is shown along with a mirror image thereof, and in output stage including a class AB bias stage, a P-channel pull-up transistor, and a N-channel pull-down transistor connected and shown to provide a rail-to-rail operational amplifier. Although not illustrated in FIG. 6, the rail-to-rail operational amplifier circuit needs bias circuitry to bias the upper and lower current mirrors in the folded cascode circuitry. The bias circuitry can be essentially the same as shown by reference in above mentioned commonly owned U.S. Pat. No. 6,150,883 to provide a bias voltage VBIAS2A on the gates of transistors A and A. As another alternative, the “floating” current source disclosed in U.S. Pat. No. 5,311,145 issued May 10, 1984 to Huijsing et al. could be used.

It should be noted that in a general sense, this invention includes a very high precision current mirror which, when incorporated into an amplifier topology as described, provides an amplifier having properties which satisfy the aforementioned unmet needs. For example, in FIG. 5A the circuitry including NMOS transistors , , , , and amplifier connected as shown can be considered to constitute a stand-alone high precision current mirror. (However, the current mirror has limited output voltage range that limits its useful as a stand-alone current mirror.)

Similarly, the portion of the circuitry in FIG. 6 including PMOS transistors A, A, A and amplifier can be considered to constitute a stand-alone high precision current mirror. In that case, the control loop including amplifier and transistors A force the drain voltages of transistors A and A to track, thereby providing very high differential output impedance and matching output currents in the drains of transistors A and A.

As indicated earlier, the open-loop gain of a multi-stage amplifier can be viewed as the product of the gains of each stage within the amplifier. The gain of each stage can be expressed as A=gmRout. In the case of the final stage or output stage, the overall amplifier gain is load-dependant because ROUT=RLOAD. The gain of prior stages, if large enough, can render the change in output stage gain due to change in load conditions insignificant compared to the open-loop gain. When a two stage topology is implemented, it is very difficult to achieve enough gain in the first stage to render the change in output stage gain due to changing load conditions insignificant. However, this difficult objective is achieved by adding the gain boost of the present invention to the first stage.

Thus, the described invention boosts the voltage gain of a differential amplifier input stage without reducing its operating speed and without any penalty of increasing noise in the amplifier, by introducing local feedback which is not part of the signal gain path to increase the equivalent output impedance of the differential amplifier.

While the invention has been described with reference to several particular embodiments thereof, those skilled in the art will be able to make the various modifications to the described embodiments of the invention without departing from the true spirit and scope of the invention. It is intended that all elements or steps which are insubstantially different or perform substantially the same function in substantially the same way to achieve the same result as what is claimed are within the scope of the invention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1A is a schematic diagram of simple prior art CMOS differential input stage.

FIG. 1B is a schematic diagram of a simple prior art CMOS differential input stage including folded cascode circuitry.

FIG. 2 is a schematic diagram of a simple prior art CMOS differential input stage coupled to folded cascode circuitry and including a gain boost amplifier.

FIG. 3 is a schematic diagram of a simple CMOS differential input stage including a gain boost amplifier according to the present invention.

FIG. 4A is a schematic diagram of an implementation of the CMOS differential input stage of FIG. 3 wherein the gain boost amplifier receives a differential voltage input signal.

FIG. 4B is a schematic diagram of an implementation of the CMOS differential input stage of FIG. 3 wherein the gain boost amplifier receives a differential current input signal.

FIG. 5A is a schematic diagram of a CMOS differential amplifier stage coupled to a folded cascode circuitry of the present invention including improved gain boost amplifier circuitry.

FIG. 5B is a schematic diagram of an implementation of the CMOS differential input stage of FIG. 5A wherein the gain boost amplifier receives a differential voltage-input signal.

FIG. 5C is a schematic diagram of a CMOS differential amplifier stage coupled to another folded cascode circuit of the present invention including improved gain boost amplifier circuitry.

FIG. 5D is a schematic diagram of an implementation of the CMOS differential input stage of FIG. 5C wherein the gain boost amplifier receives a differential current input signal.

FIG. 5E is a schematic diagram of another CMOS differential amplifier stage coupled to folded cascode circuitry including gain boost amplifier circuitry.

FIG. 6 is a schematic diagram showing implementations of the CMOS differential amplifier stage of FIG. 5A in a rail-to-rail operational amplifier.

CLAIMS

1. A differential amplifier circuit comprising: (a) first and second supply voltage rails, first and second input terminals, and an output terminal; (b) differentially connected first and second input transistors of a first channel type to the first and second input terminals; (c) a folded cascode circuit coupled to the first supply voltage rail and including a first cascode transistor and a second cascode transistor both of a second channel type, sources of the first and second cascode transistors being coupled to drains of the first and second input transistors, respectively; (d) a first load transistor of the second channel type coupled between the source of the second cascode transistor and the first supply voltage rail and a second load transistor of the second channel type coupled between the source of the first cascode transistor and the first supply voltage rail; (e) a bias source producing a bias signal on gates of the first and second cascode transistors; (f) a third cascode transistor of the second channel type having a source coupled to a drain of the second cascode transistor and a drain coupled to a first current source, a drain of the first cascode transistor being coupled to a second current source, and a voltage level shift circuit coupled between the drain of the third cascode transistor and second load transistors; and (g) a gain boost amplifier having a first input coupled to the drain of the first cascode transistor, a second input coupled to the drain of the second cascode transistor, and an output coupled to a gate of the third cascode transistor.

2. The differential amplifier circuit of claim 1 including an output stage having an input coupled to the drain of the first cascode transistor, the output stage including a pull-up transistor of the second channel type coupled between the second supply voltage rail and the output terminal, and a second output transistor of the first channel type coupled between the first supply voltage rail and the output terminal.

3. The differential amplifier of claim 2 including a class AB bias circuit coupled between a gate electrode of the pull-up and a gate electrode of the pull-down transistor.

4. The differential amplifier of claim 2 wherein the gain boost amplifier is a CMOS voltage-input differential amplifier.

5. The differential amplifier of claim 2 wherein the gain boost amplifier is a CMOS current-input differential amplifier.

6. A method of operating a differential amplifier circuit which includes first and second supply voltage rails, first and second input terminals, and an output terminal, differentially connected first and second input transistors of a first channel type to the first and second input terminals, and a folded cascode circuit coupled to the first supply voltage rail and including a first cascode transistor and a second cascode transistor both of a second channel type, sources of the first and second cascode transistors being coupled to drains of the first and second input transistors, respectively, the sources of the first and second cascode transistors also being coupled to a drain of a first load transistor and a drain of a second load transistor, respectively, the method comprising: boosting the gain of the differential amplifier circuit without introducing additional components into a signal path of the differential amplifier circuit by providing local feedback representative of an output voltage of the differential amplifier circuit to gates of the first and second load transistors by (a) coupling a drain of a third cascode transistor of the second channel type to a current source circuit and coupling a source of the third cascode transistor to a drain of the second cascode transistor; (b) coupling a drain of the third cascode transistor to gates of the first and second load transistors; and (c) driving a gate of the third cascode transistor by means of a gain boost amplifier having a first input coupled to the drain of the first cascode transistor and a second input coupled to the drain of the second cascode transistor, to accomplish the function of increasing the output impedance of the differential amplifier circuit.

7. The method of claim 6 wherein step (b) includes driving a gate of the third cascode transistor by means of a level shift circuit coupled to the drain of the third cascode transistor.

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