System and method for a scalable motion controller for controlling a plurality of servo motors

ABSTRACT

A motion control system comprises a motion unit having a motor connected to an encoder and an amplifier. The motion control system further comprises a scalable motion controller connected to the motion unit wherein the scalable motion controller receives signals from the encoder and outputs signals to the amplifier. The scalable motion controller comprises a plurality of dip sockets arranged for inserting and removing one or more motion control processors and a connector interface comprising a plurality of male and female connectors arranged for stacking a plurality of motion controllers.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

CROSS-REFERENCE TO RELATED APPLICATION

This application claims the priority benefit of U.S. Provisional Application No. 60/262,600, filed on Jan. 18, 2001, which is incorporated herein by reference.

DESCRIPTION OF THE EMBODIMENTS

Reference will now be made in detail to the present embodiments of the invention, examples of which are illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts.

FIG. 1 illustrates an exemplary motion control system comprising N motion units , where N may be any number greater than or equal to one. Each motion unit may assist in providing motion to a part of a system or apparatus, such as a robotic device, for example. Each motion unit comprises a motor , an encoder , and an amplifier . The motion control system further comprises M controllers , where M may be any number greater than or equal to one. Each controller comprises a user selectable number of motion control processors, NP. Accordingly, the i-th controller may comprise a user selectable NPi, i=1, 2, . . . M, of motion control processors. The total number of motion control processors,

may equal the number, N, of motion units .

Still further, the motion control system comprises a host computer . The host computer generally interfaces with the motion control processors via controller interfaces of the motion control processors

Each motion unit provides signals representing the motor shaft position of the corresponding motor to a corresponding motion control processor of the M controllers . Based on the actual motor shaft position of a motor and the desired motor shaft position of the motor and signals from the host computer , the corresponding motion control processor outputs signals to the motor via the corresponding amplifier driving the motor shaft of the motor to the desired position. A description of an exemplary operation of a motion control system is disclosed in a datasheet published by National Semiconductor in November 1999 entitled, “LM628/LM629 Precision Motion Controller,” which is herein incorporated by reference and which may be disclosed on the Internet at URL:http://www.national.com/pf/LM/LM628.html.

FIG. 2 illustrates an exemplary embodiment of the controller according to the present invention. Each controller comprises a controller interface , dip sockets , I/O devices , programmable logic devices , and switches SW-. The controller may also comprise other components such as resistors R-R, capacitors C-, and potentiometers VR-VR. The potentiometers VR-VR may be used for fine tuning the controller by connecting the potentiometers to corresponding inputs of operational amplifiers U, U, U, and U, for example. Capacitors C, C, C, C, C, C, C, C, C, C, C may be connected in parallel between VCC and ground. Capacitors C, C, C, C, C, C, C, and C, may be connected in parallel between +12V, for example, and ground. Capacitors C, C, C, C, C, and C may be connected between −12V, for example, and ground. Capacitors U, C, C, C may be connected between corresponding inputs of digital to analog converters U, U, U, U and ground. Capacitors C and C may be used in connection with dual monolithic multivibrators U. Capacitors C and C may be used in connection with dual monolithic multivibrators U. Various one of the resistors may be connected between inputs or outputs of the components of the controller and VCC, ground, or +12V, for example, or may be used in the design of the operation amplifiers U, U, U, and U, for example.

The dip sockets are provided for inserting and removing motion control processors from the controller . In the embodiment of FIG. 2, the dip sockets are arranged to receive up to four motion control processors. FIG. 3 illustrates the controller with four motion control processors inserted in the dip sockets . In other embodiments of the controller , the dip sockets may be arranged to receive more or less motion control processors. The dip sockets may be of any shape or size so long as it is capable of inserting and removing the motion control processors from the controller . For example, the dip socket may be designed to received processors having a quad flatpack (QFP) design or any other chip packaging design. In an alternate embodiment, other receptacles may be use in place of the dip sockets to receive the motion control processors. For example, any physical connector that is capable of connecting the motion control processors directly or indirectly to the controller may be used in the place of the dip sockets.

In one embodiment, the motion control processors correspond to the LM628 or LM629 motion control processors manufactured by National Semiconductor. However, other motion control processor may be used. It will be obvious to those of ordinary skills in the art how to alter the controller to receive other motion control processors.

The controller connects the controller interface , the programmable logic devices , and the motion control processors . The controller interface connects with the host computer and receives signals from the host computer , which are provided to the programmable logic devices and the motion control processors . The controller interface also receives signals from the programmable logic devices and the motion control processors , which are provided to the host computer .

In one embodiment, the controller interfaces of the controllers are capable of connecting to each other in a stacking manner, i.e., one on top of the other. Each controller interface may comprise one or more female connectors on a component side of the controller and one or more male connectors on a pin protrusion side of the controller . In this arrangement, a first controller may connect with a second controller on the component side of the first controller by connecting the female connectors of the controller interface of the first controller with the male connectors of the controller interface of the second controller. Further, in this arrangement, the first controller may connect with a third controller on the pin protrusion side of the first controller by connecting the male connectors of the controller Interface of the first controller with the female connectors of the controller Interface of the third controller . Accordingly, the controllers may be connected by stacking one controller on top of another.

Alternatively, the controller interfaces may comprise one or more male connectors on the component side of the controllers and one or more female connectors on the pin protrusion side of the controllers . The controller interface may be arranged according to the PC/104 form factor. The PC/104 specification, version 2.4, August 2001, is disclosed at the following URL: http:/www.pc104.org/technology/PDF/PC104Specv246.pdf, which is herein incorporated by reference.

More particularly, the controller interface may comprise two buses J and J having a total of 104 signal contacts. Bus J may have 64 signal contacts and bus J may have 40 signal contacts. In one embodiment of the present invention, the entire controller is PC/104 “Compliant.” That is, the entire controller conforms to all non-optional aspects of the PC/104 specification, including both mechanical and electrical specifications. For example, the controller has a form-factor of 3.550 by 3.775 inches (90 by 96 mm) and a 16 bit PC/AT bus implemented via “stackthrough” bus connectors.

By providing dip sockets for inserting and removing motion control processors, the controller is scalable and may be adapted for any motion control system requiring any number of motion control processors. If the number of processors needed in a motion control system exceeds the number of motion control processors capable of being added to a single controller , one or more additional processors may be added to one or more additional controllers that are connected together via the controller interfaces . For example, assume that the controller may support up to four motion control processors and that a motion control system requires five motion control processors. Two controllers may be stacked together with the first controller having four processors and the second controller having one processor. A user is not required to purchase two controllers having a total of eight processors fixed to the controllers (i.e., four processors fixed to each controller), for example. Therefore, there is significant cost savings in not having to purchase three motion control processors that are not going to be used.

FIG. 4 illustrates an exemplary circuit diagram of the controller . The circuit diagram includes a part of the controller interface , the programmable logic devices , and the motion control processors . In this embodiment, the motion control processors correspond to the LM628 motion control processors manufactured by National Semiconductor. However, changing the circuit diagram of FIG. 4 for other motion control processors will be obvious to those of ordinary skill in the art. As shown in FIG. 4, the data lines of the controller interface connect to the data port inputs (i.e., pins -) of the LM628 motion control processors . The data lines of the controller interface receive data and commands from the host processor and transmit the data and commands to the data port inputs of each of the motion control processors

Further, the address lines of the controller interface connect to each of the programmable logic devices . The address lines receive address information from the host computer and transmit the address information to each of the programmable logic devices . The line of the address lines corresponding to the least significant bit of the address information received from the host computer connects to the port select input of each motion control processor

The programmable logic devices decode the address information and output chip select signals to the chip select inputs of the motion control processors , respectively for writing and reading data operations. Each motion control processor is associated with an address that may be selected by a user via the switches SW, SW, SW, SW, respectively. The programmable logic devices are programmed to process the address received from host computer via the controller interface to determine whether the address corresponds to the address of the corresponding motion control processor provided by corresponding switches SW, SW, SW, SW. Each of the programmable logic devices outputs appropriate signals to the chip select input of the corresponding motion processor selecting that processor, if the address received from the host computer via the controller interface corresponds to the address of the corresponding motion control processor. In this way, typically, only one motion processor is selected. However, by providing a programmable logic device U and a shift register U, as shown in FIG. 4, two or more processors may be selected at the same time for coordinated motion. Shift register U outputs a corresponding chip select output signal for each of the programmable logic devices . These chip select output signals are output by the programmable logic devices to the chip select input of the corresponding motion processor. Two or more processors may be selected at the same time for coordinated motion if the shift register U outputs two or more appropriate output chip select signals for selecting the corresponding two or more motion control processors. For example, to achieve coordinated motion for the axis represented by control processor and the axis represented by control processor , the shift register U may output a low output signal to programmable logic device and , which passes these signals to the chip select input of motion control processors and , thereby selecting the corresponding axes for coordinated motion. The shift register U outputs a high output signal to programmable logic device and so that motion control processors and are not selected.

The shift register U determines which motion control processors to select for coordinated motion based on information received from the host processor via selected ones of the lines of data lines , for example, the lines representing the four most significant bits of data information received for the host processor . The selected lines of data lines transmit chip select information for the corresponding motion control processor. Accordingly, to achieve coordinated motion for the axis represented by control processor and the axis represented by control processor , for example, the corresponding selected lines of data lines may transmit low output signals to be loaded in the shift register U for output to the programmable logic device and at an appropriate time, as determined by programmable logic device U. The corresponding selected lines of data lines may transmit high output signals to be loaded in the shift register U for output to the programmable logic device and at an appropriate time, as determined by programmable logic device U.

The programmable logic device U transmits a signal to shift register U causing the signals loaded in the shift register to be output to the corresponding programmable logic devices based on the address information provided by SW and the address information received from the host computer via address lines and based on an address enable signal provided by the host computer via the controller interface . If the address information provided by SW equals the address information received from the host computer via address lines and the address enable signal is low, then the programmable logic device outputs a signal to the shift register U causing the signals loaded in the shift register to be output to the corresponding programmable logic devices . In an alternate embodiment, any other storage device may be used in place of the shift register U.

The reset line of the controller interface connects to each of the programmable logic devices . The reset line receives reset signals from the host computer and transmits the reset signals to each of the programmable logic devices . The programmable logic devices further receive longpulse input signals LP, respectively, from dual monolithic multivibrators U and U, as shown in FIG. . In one embodiment, the dual monolithic multivibrators U and U correspond to the SN74LS221 dual monolithic multivibrators manufactured by Texas Instruments. A single dual monolithic multivibrator produces two longpulse signals. Accordingly, two dual monolithic multivibrators U and U may be used to provide the longpulse input signals to the programmable logic devices . Based on the longpulse input signals and the reset signals received for the host processor via the reset line , the programmable logic devices output reset signals to the reset inputs of the motion control processors , respectively. In one embodiment, when the longpulse input signal is high (logic 1) and the reset signal is low (logic 0), the reset signal output from the programmable logic device is high (logic 1), resetting the corresponding motion control processor to a predetermined internal condition. If these input conditions are not met, the reset signal output from the programmable logic device is low (logic 1).

The write line of the controller interface connects to the write input of each of the motion control processors and the read line of the controller interface connects to the read input of each of the motion control processors

Programmable logic device receives a host interrupt signal from a host interrupt output of each of the motion control processors and the information from the data lines of the controller interface . The programmable logic device outputs IRQ signals to the controller interface via a switch SW, which distinguishes the controller from other controllers.

Returning to FIG. 2, the I/O devices connect the motion units and corresponding motion control processors . The I/O devices receive signals from the encoders of corresponding motion units and deliver the signals to the corresponding motion control processors . Further, the I/O devices output signals from the corresponding motion control processors to the amplifiers of the corresponding motion units .

FIG. 5 illustrates an exemplary circuit diagram of a part of the controller , which includes the I/O device and the corresponding motion control processor . In one embodiment, circuit diagrams for I/O devices and the corresponding motion control processors , respectively, are similar to the circuit diagram of FIG. . As shown in FIG. 5, the I/O device receives signals from the encoder of the corresponding motion unit and delivers the signals to the motion control processor . If the motion control processor corresponds to the LM628 or LM629 motion control processors manufactured by National Semiconductor, the I/O device may deliver the signals from the encoder to pins , , and of the LM628 or LM629 motion control processor . The signals from the I/O device may undergo processing by differential-input line receivers prior to being received by the motion control processor , as shown in FIG. . In one embodiment, the differential-input line receivers correspond to the differential-input line receivers of the MC3486 quadruple differential line receivers manufactured by Texas Instruments. The MC3486 quadruple differential line receiver from Texas Instrument comprises four differential-input line receivers. Accordingly, because only three differential-input line receivers of the MC3486 quadruple differential line receivers are used to process signals from the I/O device , the MC3486 quadruple differential line receiver may receive and process signals from at least one of the other I/O devices

FIG. 6 illustrates an exemplary circuit diagram of a part of the controller of FIG. 2 for the I/O devices and the motion control processors when the differential-input line receivers correspond to the differential-input line receivers of the MC3486 quadruple differential line receivers U, U, U manufactured by Texas Instruments. As shown in FIG. 6, the line receivers U, U, U receives signals from the I/O device , in addition to signals from I/O device , respectively.

Further, as illustrated in FIG. 5, the I/O device receives signals from the motion control processor and outputs the signals to the amplifier of the corresponding motion unit . As shown in FIG. 5, the signals from the motion control processor may undergo processing prior to being received by the I/O device . For example, if the motion control processor outputs digital signals corresponding to or similar to the output signals of the LM628 motion control processor manufactured by National Semiconductor, the signals output from the motion control processor may be processed by a digital to analog converter and an operational amplifier prior to being received by the I/O device

FIG. 6 illustrates an exemplary circuit diagram of a part of the controller of FIG. 2 when the motion control processors output digital signals corresponding to or similar to the output signals of the LM628 motion control processor manufactured by National Semiconductor. As shown in FIG. 6, the signals from the motion control processors are processed by digital to analog converters I/O, U, U, and U, and operational amplifiers U, U, U, and U, respectively, prior to being received by the I/O devices . The digital to analog converters U, U, U, and U may correspond to the DAC0800LCM digital to analog converters manufactured by National Semiconductor. The operational amplifiers U, U, U, and U may correspond to the UA741CD operation amplifiers manufactured by Philips Semiconductors. If the output of the motion control processors correspond to or are similar to the output signal of the LM629 motion control processor manufactured by National Semiconductor, then the output of the motion control processors maybe input directly to the I/O device

The motion controller may further comprise an integrated component for a software language motion program to communicate with the motion control processors . The software language motion program may provide a software library that provides a level of abstraction for a software engineer or programmer to facilitate rapid development of motion control software associated with controlling the motors of the motion control system without having to write device level software to communicate with the motion control processors installed on the motion controller . The library may provide high level function calls for initialization, PID filter set up, motion control, status reporting, and coordinated motion control. This allows more rapid development of the motion control system. The library may contain the following function prototypes for the LM628 or LM629 motion control processors manufactured by National Semiconductor. However, it will be obvious to those of ordinary skills in the art to change the following library function for other motion control processors:

Initialization

Initialize_LM62X(int address, int dac—12_bit_flag);

Reinitialize_LM62X_Soft_Reset(int address, int dac—12_bit_flag);

Hardware_Reset_LM62X(int address);

Reset(int address);

Define_Home(int address)

PID Filter

KP_Pid_Designate(int address, long int derivative_sampling_interval_us, int kp_data, int fclk_mhz);

KP_Pid_Designate(int address, long int derivative_sampling_interval_us, int ki_data, int fclk_mhz);

KP_Pid_Designate(int address, long int derivative_sampling_interval_us, int kd_data, int fclk_mhz);

IL_Pid_Designate(int address, long int derivative_sampling_interval_us, int il_data, int fclk_mhz);

Motion

Start_Motion(int address)

Acceleration_Relative(int address, unsigned log int accelaration_data_cts_sec_sec, int fclk_mhz)

Acceleration_Absolute(int address, unsigned log int accelaration_data_cts_sec_sec, int fclk_mhz)

Forward_Velocity_Relative_Move(int address, unsigned long int velocity_data_cts_sec, int fclk_mhz)

Reverse_Velocity_Relative_Move(int address, unsigned long int velocity_data_cts_sec, int fclk_mhz)

Position_Relative_Move(int address, unsigned long int velocity_data_cts_sec, int fclk_mhz)

Position_Absolute_Move(int address, unsigned long int velocity_data_cts_sec, long int position_cts, int fclk_mhz)

Stop_Motor_Smoothly(int address,)

Stop_Motor_Abruptly(int address,)

Turn_Off_Motor(int address,)

Interrupt

Record_Index_Position(int address,)

Interrupt_On_Error(int address, unsigned int position_error_threshold)

Stop_On_Error(int address, unsigned int position_error_threshold)

Set_Breakpoint_Absolute(int address, long int position_breakpoint)

Set_Breakpoint_Relative(int address, long int position_breakpoint)

Mask_Interrupts(int address, int breakpoint_irq_on, int position_error_irq_on, int wrap_around_irq_on, int index_pulse_irq_on, int trajectory_complete_irq_on, int command_error_irq_on)

First_Interrupts(int address, int breakpoint_irq_rst, int position_error_irq_rst, int wrap_around_irq_rst, int index_pulse_irq_rst, int trajectory_complete_irq_rst, int command_error_irq_rst)

Reporting

Read_Status_Byte(int address, int *status);

Read_Signals_Register(int address, unsigned int *signals);

Read_Index_Position(int address, long int *index_position)

Read_Desired_Position (int address, long int *desired_position)

Read_Real_Position(int address, long int *real_position)

Read_Desired_Velocity(int address, long int *desired_velocity)

Read_Real_Velocity(int address, long int *real_velocity)

Read_Integration_Sum(int address, unsigned int *integration_sum)

Coordinated Motion

Coordinated_Move_Resgister_Load(int address, int a_motor_select_flag, int b_motor_select_flag, int c_motor_select_flag, int d_motor_select_flag)

Other embodiments of the invention will be apparent to those skilled in the art from consideration of the specification and practice of the invention disclosed herein. It is intended that the specification and examples be considered as exemplary only, with a true scope and spirit of the invention being indicated by the following claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate several embodiments of the invention and together with the description, serve to explain the principles of the invention.

FIG. 1 illustrates an exemplary motion control system.

FIG. 2 illustrates an embodiment of a controller according to the present invention.

FIG. 3 illustrates the controller of FIG. 2 with exemplary motion control processors inserted in the dip sockets.

FIG. 4 illustrates an exemplary circuit diagram of a part of the controller of FIG. 2 including an exemplary controller interface, exemplary programmable logic devices, and exemplary motion control processors.

FIG. 5 illustrates a first embodiment of a circuit diagram of a part of the controller of FIG. 2 including an exemplary I/O device and an exemplary corresponding motion control processor connected to an exemplary corresponding motion unit.

FIG. 6 illustrates a second embodiment of a circuit diagram of a part of the controller of FIG. 2 including multiple I/O devices and exemplary corresponding motion control processors connected to exemplary corresponding motion units.

CLAIMS

1. A scalable motion controller for controlling a plurality of servo motors in a motion control system, the scalable motion controller comprising: means for inserting and removing one or more motion control processors from the scalable motion controller; and means for stacking a plurality of scalable motion controllers.

2. The scalable motion controller of claim 1, wherein the scalable motion controller is PC/104 compliant.

3. The scalable motion controller of claim 1, further comprising means for selecting a plurality of motion control processors for coordinated motion.

4. A motion control system comprising: a motion unit wherein the motion unit comprises a motor connected to an encoder and an amplifier; and a scalable motion controller connected to the motion unit wherein the scalable motion controller receives first signals from the encoder and outputs second signals to the amplifier, wherein the scalable motion controller comprises means for inserting and removing one or more motion control processors from the scalable motion controller.

5. The motion control system of claim 4, wherein the scalable motion controller comprises a plurality of dip sockets arranged for inserting and removing one or more motion control processors.

6. The motion control system of claim 4, wherein the scalable motion controller comprises a connector interface comprising a plurality of male and a plurality of female connectors arranged for stacking a plurality of motion controllers.

7. The motion control system of claim 4, wherein the scalable motion controller comprises means for stacking a plurality of scalable motion controllers.

8. The motion control system of claim 4, wherein the scalable motion controller is PC/104 compliant.

9. The motion control system of claim 4, wherein the scalable motion controller comprises means for selecting a plurality of motion control processors for coordinated motion.

10. The motion control system of claim 4, wherein the scalable motion controller comprises: a plurality of programmable logic devices wherein each of the plurality of programmable logic devices provides a chip select signal to a chip select input of a corresponding motion control processor; a storage device for storing the chip select signals for each of the plurality of programmable logic devices; and a coordinated motion device for causing the storage device to output the chip select signals to the plurality of programmable logic devices at substantially the same time based on a coordinated motion address.

11. The motion control system of claim 10, wherein the storage device is a shift register.

12. A scalable motion controller for controlling a plurality of servo motors in a motion control system, the scalable motion controller comprising: a plurality of dip sockets arranged for inserting and removing one or more motion control processors; and a connector interface comprising a plurality of male and a plurality of female connectors arranged for stacking a plurality of scalable motion controllers.

13. The scalable motion controller of claim 12, wherein the scalable motion controller is PC/104 compliant.

14. The scalable motion controller of claim 12, further comprising: a plurality of programmable logic devices wherein each of the plurality of programmable logic devices provides a chip select signal to a chip select input of a corresponding motion control processor; a storage device for storing the chip select signals for each of the plurality of programmable logic devices; and a coordinated motion device for causing the storage device to output the chip select signals to the plurality of programmable logic devices at substantially the same time based on a coordinated motion address.

15. The scalable motion controller of claim 14, wherein the storage device is a shift register.

COPYRIGHT

User acknowledges that Fairview Research and its third party providers retain all right, title and interest in and to this xml under applicable copyright laws. User acquires no ownership rights to this xml including but not limited to its format. User hereby accepts the terms and conditions of the License Agreement.