Adjustable compensation of a piezo drive amplifier depending on mode and number of elements driven

ABSTRACT

An integrated circuit () provides drive signals to a piezo element () of a milli-actuator device () in a mass data storage device (). The integrated circuit () includes a circuit () for selectively operating the integrated circuit () in either a voltage or a charge mode of operation. A first amplifier circuit () can be compensated for a variable number of piezo elements in the charge mode of operation by adjustable output impedance adjusting elements () that are switchably connectable into the amplifier circuit ().

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

CROSS REFERENCE TO RELATED APPLICATIONS

This is a continuation-in-part of U.S. patent application Ser. No. 09/681,695 filed May 22, 2001.

DETAILED DESCRIPTION

FIG. 1 is a block diagram of a generic disk drive system , which represents the general environment in which the invention may be practiced. The system includes a magnetic media disk that is rotated by a spindle motor and spindle driver circuit . A data transducer or head is locatable along selectable radial tracks (not shown) of the disk by a voice coil motor , along a gross radial position. A milli-actuator may be co-located with the head on the end of the arm . The milli-actuator is preferably of the type that employs a piezo element for the fine positioning of the head , such devices being known in the art. (Although a piezo element type milli-actuator is preferably used, it should be understood that other types of milli-actuator devices may be equally advantageously employed.) The motion of the milli-actuator may be a displacement to the left or right of the axis of the arm , to provide fine radial positioning of the head along the track sought to be followed.

The radial tracks may contain magnetic states that contain information about the tracks, such as track identification data, location information, synchronization data, as well as user data, and so forth. The head is used to both record user data to and read user data back from the disk . The head also detects signals that identify the tracks and sectors at which data is written, and to detect servo bursts that enable the head to be properly laterally aligned with the tracks of the disk, as known.

Analog electrical signals that are generated by the head in response to the magnetic signals recorded on the disk are preamplified by a preamplifier for delivery to read channel circuitry . The servo signals detected from the track being followed are detected and demodulated by one or more servo demodulator circuits and processed by a digital signal processor (DSP) to control the gross and fine positions of the head via a positioning driver circuit . In the past, the servo data would that is read and processed has been analog data that has been interpreted by the DSP for positioning the head .

A microcontroller is typically provided to control the DSP as well as the interface controller to enable data to be passed to and from the host interface (not shown) in known manner. A data memory may be provided, if desired, to buffer data being written to and read from the disk .

FIG. 2 is an electrical schematic diagram of a portion of the positioning driver circuit , illustrating the overall structure of a milli-actuator circuit , according to a preferred embodiment of the invention. The milli-actuator circuit may be constructed, if desired, on a single integrated circuit chip , as shown, together with other associated circuitry, for example, the voice coil driving circuitry and other positioning driver circuitry , as well as servo circuitry of the spindle driver , and so forth.

The milli-actuator driver circuitry includes two operational transconductance amplifiers (OTAs) stages and to provide milli-actuator driving output signals to control an associated piezo element through an external mirror circuit . The output from amplifier is connected to the input of amplifier by line . It should be noted that although the piezo element may have a number of positioning elements in practice, only a single element is shown in the drawings for convenience. As will become apparent, the circuit selectively provides either voltage mode or charge mode control of the milli-actuator. The input to the first stage amplifier may be, for example, on lines and from a digital to analog converter (not shown) driven by the DSP to control the piezo element of the milli-actuator.

The first OTA is preferably operated in Class A mode, while the second OTA is preferably operated in Class AB mode. The output of the second OTA has three outputs, below described in detail, which provide a 1× output to the sense capacitor in charge mode, and two n× outputs and to the external current mirror in voltage mode. The multiple “n” of the n× outputs may be as needed for the particular application; for example, in one embodiment n may be 10 to provide a 10× output, and in another embodiment, n may be 6.125 to provide a 6.125× output.

A decoder is provided to decode signals indicating the desired mode of operation of the milli-actuator driving circuit , as well as the number of piezo elements that are being driven. The data may be provided, for example, from data that is inputted to the serial port (not shown) of the mass data storage device, to be decoded by the decoder . In a preferred embodiment, the decoder may be, for example, merely a memory element into which configuration data is held from the initializing serial port data provided by the mass data storage device manufacturer.

The current or voltage mode of the circuit is controlled by a mode selection circuit that includes two MOS transistors and , which have a selection signal from the decoder applied to their respective gates on lines and .

Thus, when driving the piezo motor in voltage mode, the 1× output of the OTA is disabled and the n× output is used to create a voltage feedback loop through MOS transistor . In charge mode, MOS transistor conducts, coupling the n× output to analog ground, AGND . Also, in current mode, signals are provided on control lines to the Class A amplifier to control its impedance, as below described in detail.

In charge mode operation, a voltage feedback loop is formed with the 1× output driving the external sense capacitor , and the piezo element is driven by the n× outputs and . The charge delivered to the piezo element is determined by the ratio of the capacitance of the piezo element and the sense capacitance, the n× current drive ratio, and the voltage applied to the OTA from the voltage source VM . The voltage source VM is referenced to analog ground .

The external mirror can be implemented with bipolar or MOS devices that support the output range needed for the particular piezo element employed. As mentioned, the piezo element may have a number of positioning elements. Series resistors may be used, if desired, to improve the matching characteristics of the mirror.

With reference now additionally to FIGS. 3A-B, a detailed schematic of the amplifier is shown. The amplifier is implemented with CMOS devices, and, as shown, operated between a predetermined positive voltage, in this case conveniently, VM, and analog ground, AGND. As mentioned, the amplifier is preferably operated in Class AB mode. Thus, input resistors and are provided to limit the Class AB mode current during switch over.

The circuit includes a shut-off circuit that turns off the 1× output and drives it to a high impedance, for example, when the circuit is operated in voltage mode. A calibration circuit , as shown, provides inputs to the circuit on lines and . The 1× output is provided on output line by pull-up and pull-down transistors and , which are constructed in wells and that are connected respectively to AGND and VM. Thus, the maximum voltage that is applied across the 1× output driver transistors is the difference between VM and AGND, enabling the transistors of the drivers to be integrated onto the same integrated circuit chip as other components of the motor controlling circuitry. Outputs to the n× driver circuits, shown in detail in FIG. 3B, are provided in voltage mode of operation on output lines and .

With reference additionally now to FIG. 3B, the details of the n× amplifiers and and the remaining calibration circuitry are shown. It should be noted that the voltage of the n× amplifiers and may be other than the voltage VM of the 1× amplifier; however, they are also referenced to the analog ground potential, AGND.

Details of the external mirror and capacitor are shown in FIG. 3C, to which reference is now additionally made. The mirror receives the outputs from the n× and 1× drivers on respective lines , , and . The mirror circuit is shown as being constructed of bipolar devices; however, it should be understood that MOS devices may be equally advantageously employed.

It can be seen that through the use of mirrors that are biased to a predetermined voltage with respect to ground, the milli-actuator circuit can be easily integrated in an integrated circuit with the wells containing the driver transistors biased to a substrate ground, which may be the analog ground for the circuit. The integration of these components enables the entire circuit to be combined with other integrated circuitry, such as the motor servo, or other desired circuitry. This results in a reduction on the load on the high voltage-switching regulator and reduces the number of required external components.

Details of the Class A amplifier are shown in the electrical schematic diagram of FIGS. 4A-B, to which reference is now additionally made. One of the salient problems addressed by the invention is that the gain of the amplifier is variable in charge mode; however, the stability and bandwidth of the amplifier must remain essentially the same. This accomplished by selectively switching impedances into the circuit to maintain the output impedance to make the amplifier self-adjusting for the closed loop gain with essentially the same bandwidth in the current mode of operation.

To this end, the amplifier receives control signals from the decoder on lines to control the impedance of the circuit. More particularly, the circuit includes three chains , , and of diode connected MOSFETs to establish the high-end impedance of the circuit. Chain is normally on to set an nominal initial impedance or load, and chains and may be selectively turned on by initialization signals from the decoder via respective amplifiers and to compensate for the largest anticipated gain of the circuit. Thus, for example, a typical impedance range of a Class A amplifier of the type described is between about 39 Kohms and 150 Kohms. The high-end range is determined by the combination of the changes ,, and by control signals on lines .

Additionally, with reference particularly to FIG. 4A, the input differential amplifier receives the input signals INM and INP on respective lines and . Normally load transistors and are provided on the respective source and drain sides of the amplifier . By control signals on lines from the decoder , however, additional load circuits - may be selectively connected in parallel with the normal load transistors and . Thus, the impedance of the amplifier may be widely controlled, in dependence on the control signals provided on lines .

Although MOSFET devices are shown, it should be understood that resistors that are selectively switched into or out of the circuit can be alternatively used. MOSFET devices are preferred because they when integrated onto an integrated circuit chip, they occupy less space than an integrated resistor. The MOSFET devices are designed to provide the desired resistance necessary to enable the overall impedance of the circuit to be selectively adjusted, as desired.

Although the invention has been described and illustrated with a certain degree of particularity, it is understood that the present disclosure has been made only by way of example, and that numerous changes in the combination and arrangement of parts can be resorted to by those skilled in the art without departing from the spirit and scope of the invention, as hereinafter claimed.

BRIEF DESCRIPTION OF DRAWINGS

The invention is illustrated in the accompanying drawings, in which:

FIG. 1 is a block diagram of a mass data storage device, illustrating the environment of the invention.

FIG. 2 is an electrical schematic diagram of a portion of the milli-actuator circuit, according to a preferred embodiment of the invention.

FIGS. 3A and 3B are detailed electrical schematic diagrams showing details of the output drivers of the Class AB output amplifier of FIG. .

FIG. 3C is an electrical schematic diagram of externally connected components, including a piezo element driving mirror and a charge measuring capacitor for use with the circuit of FIGS. 3A and 3B.

FIGS. 4A and 4B are an electrical schematic diagram of a class A amplifier used in the circuit of FIG. 2, including a circuit for adjusting the output impedance of the circuit depending upon the number of piezo elements in the piezo positioning devices driven and the mode of operation of the circuit, according to a preferred embodiment of the invention.

In the various figures of the drawing, like reference numerals are used to denote like or similar parts.

CLAIMS

1. An integrated circuit for providing drive signals to a piezo element of a milli-actuator device in a mass data storage device, comprising: a driving circuit for selectively driving said piezo element in either a voltage mode or a charge mode; and a circuit for compensating said driving circuit for a variable number of piezo elements in a charge mode of operation and providing a compensating feedback signal in a voltage mode of operation.

2. The integrated circuit of claim 1 wherein said circuit for compensating said driving circuit for a variable number of piezo elements in a charge mode of operation comprises a circuit for adjusting an output impedance of at least a portion of said driving circuit.

3. The integrated circuit of claim 2 wherein said circuit for adjusting an output impedance of at least a portion of said driving circuit comprises a plurality of resistance providing elements that are selectively switched into the circuit.

4. The integrated circuit of claim 3 wherein said resistance providing elements comprise a plurality of series connected MOSFET devices.

5. The integrated circuit of claim 3 wherein said resistance providing elements comprise a plurality of integrated resistors.

6. The integrated circuit of claim 1 further comprising a circuit for containing command data to specify a mode of operation of said integrated circuit.

7. The integrated circuit of claim 6 further comprising circuitry for configuring said integrated circuit to operate in a voltage mode or a charge mode in response to said command data to specify a mode of operation of said integrated circuit.

8. The integrated circuit of claim 6 wherein said integrated circuit further comprising circuitry for configuring a parameter of said integrated circuit to compensate for said number of piezo element devices.

9. A method for providing drive signals to a piezo element of a milli-actuator device in a mass data storage device, including a variable number of piezo element devices, comprising: selectively driving said piezo element in either a voltage mode or a charge mode; and compensating said driving circuit for said variable number of piezo element devices in a charge mode of operation and providing a compensating feedback signal in a voltage mode of operation.

10. The method of claim 9 wherein said compensating said driving circuit for a variable number of piezo element devices in a charge mode of operation comprises adjusting an output impedance of at least a portion of said driving circuit.

11. The method of claim 10 wherein said adjusting an output impedance of at least a portion of said driving circuit comprises selectively switching a plurality of resistance providing elements into the circuit.

12. The method of claim 11 wherein said selectively connecting a plurality of resistance providing elements into the circuit comprises selectively connecting a plurality of series connected MOSFET devices into the circuit.

13. The method of claim 11 wherein said selectively connecting a plurality of resistance providing elements into the circuit comprises selectively connecting a plurality of resistors into the circuit.

14. The method of claim 9 further comprising containing command data to specify a mode of operation of said integrated circuit.

15. The method of claim 14 further comprising configuring said integrated circuit to operate in a voltage mode or a charge mode in response to said command data.

16. The method of claim 15 wherein said configuring a parameter of said integrated circuit to compensate for said number of piezo element devices comprises configuring an impedance of at least a portion of said integrated circuit.

17. An integrated circuit for providing drive signals to a piezo element of a milli-actuator device in a mass data storage device, said piezo element including a variable number of piezo element devices, comprising: means for selectively driving said piezo element in either a voltage mode or a charge mode; and means for compensating said driving circuit for said variable number of piezo element devices in a charge mode of operation and providing a compensating feedback signal in a voltage mode of operation.

18. The integrated circuit of claim 17 wherein said means for compensating said driving circuit for a variable number of piezo element devices in a charge mode of operation comprises means for adjusting an output impedance of at least a portion of said driving circuit.

19. The integrated circuit of claim 18 wherein said means for adjusting an output impedance of at least a portion of said driving circuit comprises means for selectively switching a plurality of resistance providing elements into the circuit.

20. The integrated circuit of claim 19 wherein said means for selectively connecting a plurality of resistance providing elements into the circuit comprises means for selectively connecting a plurality of series connected MOSFET devices into the circuit.

21. The integrated circuit of claim 19 wherein said means for selectively connecting a plurality of resistance providing elements into the circuit comprises means for selectively connecting a plurality of resistors into the circuit.

22. The integrated circuit of claim 17 further comprising means for containing command data to specify a mode of operation of said integrated circuit.

23. The integrated circuit of claim 22 further comprising means for configuring said integrated circuit to operate in a voltage mode or a current mode in response to said command data.

24. The integrated circuit of claim 23 wherein said means for configuring a parameter of said integrated circuit to compensate for said number of piezo element devices comprises means for configuring an impedance of at least a portion of said integrated circuit.

25. A mass data storage device, comprising: an integrated circuit for providing drive signals to a piezo element of a milli-actuator device in a mass data storage device, said integrated circuit including: a driving circuit for selectively driving said piezo element in either a voltage mode or a charge mode; and a circuit for compensating said driving circuit for a variable number of piezo elements in a charge mode of operation and providing a feedback signal in a voltage mode of operation.

26. The mass data storage device of claim 25 wherein said circuit for compensating said driving circuit for a variable number of piezo elements in a charge mode of operation comprises a circuit for adjusting an output impedance of at least a portion of said driving circuit.

27. The mass data storage device of claim 26 wherein said circuit for adjusting an output impedance of at least a portion of said driving circuit comprises a plurality of resistance providing elements that are selectively switched into the circuit.

28. The mass data storage device of claim 27 wherein said resistance providing elements comprise a plurality of series connected MOSFET devices.

29. The mass data storage device of claim 27 wherein said resistance providing elements comprise a plurality of integrated resistors.

30. The mass data storage device of claim 25 further comprising a circuit for containing command data to specify a mode of operation of said integrated circuit.

31. The mass data storage device of claim 30 further comprising circuitry for configuring said integrated circuit to operate in a voltage mode or a current mode in response to said command data to specify a mode of operation of said integrated circuit.

32. The mass data storage device of claim 30 wherein said mass data storage device further comprising circuitry for configuring a parameter of said integrated circuit to compensate for said number of piezo element devices.

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