Ferroelectric capacitor with electrode formed in separate oxidizing conditions

ABSTRACT

A method of fabricating a ferroelectric capacitor comprises the steps of forming an upper electrode on a ferroelectric film formed on a lower electrode by a sputtering process of a conductive oxide film, wherein the sputtering process is conducted by using a metal target under a first, oxidizing condition and a second, less oxidizing condition.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE INVENTION

[First Embodiment]

FIG. 2 shows the construction of a ferroelectric capacitor according to a first embodiment of the present invention.

Referring to FIG. 2, a Si substrate carries thereon a CMOS structure, and a CVD oxide film is formed on the Si substrate so as to bury the CMOS structure underneath. On the CVD oxide film , a Ti adhesion layer is deposited by a sputtering process with a thickness of about 20 nm, and a lower electrode of Pt is formed on the Ti adhesion layer also by a sputtering process with a thickness of about 175 nm. TABLE I below summarizes the sputtering condition of the Ti adhesion layer and the lower electrode .

It should be noted that the lower electrode is by no means limited to Pt but may be formed of Ir or Ru or a conductive oxide thereof such as RuO2 or SrRuO3.

On the lower electrode , a ferroelectric capacitor insulation film of PZT or PLZT is formed by an R.F. sputtering process with a thickness of about 200 nm under a condition summarized in TABLE II below.

The capacitor insulation film thus formed is then subjected to a crystallization process by applying a rapid thermal annealing (RTA) process at 600° C. for a 60 seconds in an Ar atmosphere containing O2 with a concentration less than about 5%, followed by an oxygen compensating process conducted at 750° C. for 60 seconds for compensation of any oxygen defects.

After the formation of the ferroelectric capacitor insulation film , an upper electrode of IrO2 is formed on the capacitor insulation film under the condition summarized in TABLE III below.

Hereinafter, a preliminary explanation of the present embodiment will be given with reference to FIGS. 3 and 4, wherein FIG. 3 shows the optical reflectance of the IrO2 electrode layer thus formed under the condition of TABLE 3 while changing the oxygen flow-rate and the Ar flow-rate variously.

Referring to FIG. 3, it can be seen that the reflectance of the IrO2 electrode layer decreases with increased proportion of oxygen in the sputtering atmosphere, indicating that the proportion of IrO2 in the layer increases as a result of progress of oxidation of Ir. In other words, the relationship of FIG. 3 indicates that the reflectance of the IrO2 electrode layer can be used as the index of degree of oxidation of the IrO2 electrode layer .

FIG. 4, on the other hand, shows the optical reflectance of the IrO2 electrode layer for the case in which the sputtering power is changed variously while maintaining the same sputtering atmosphere.

Referring to FIG. 4, it can be seen that the optical reflectance increases with increasing sputtering power, indicating that there occurs a reduction in the electrode layer when the sputtering power is increased and that the electrode layer is primarily formed of metal Ir. When the sputtering power is set low, on the other hand, there occurs an oxidation in the IrO2 electrode layer during the sputtering process thereof.

The result of FIGS. 3 and 4 indicates clearly that it is preferable to use a low sputter power and associated oxidizing atmosphere when forming the upper electrode by IrO2.

FIG. 5 shows the relationship between the switching electric charge Qsw of the ferroelectric capacitor thus formed and the sputtering power used for forming the IrO2 upper electrode .

Referring to FIG. 5, it can be seen that a large switching electric charge Qsw is obtained for the ferroelectric film underneath the electrode layer when the sputtering power used for forming the IrO2 electrode layer is set low. This phenomenon indicates that the sputtering atmosphere has changed to become more oxidizing as a result of the use of the low sputtering power and the oxidizing atmosphere thus realized has suppressed the reduction of the ferroelectric film .

FIG. 6 shows the surface state of the electrode layer observed by electron microscopy for the case in which the electrode layer is sputtered consecutively on a number of substrates while setting the sputtering power to 1 kW in accordance with the condition of TABLE III. In FIG. 6, the electrode layer is formed with a thickness of 200 nm.

According to the experiment, the substrate temperature increases gradually with the progress of the sputter deposition on the substrates, and because of the gradual rise of the substrate temperature, it was observed that giant IrO2 crystals having a needle shape as represented in FIG. 6 start to appear after the 25th deposition, wherein FIG. 6 shows the case in which the sputter deposition was conducted with the sputtering power of 1 kW such that the IrO2 electrode layer has the thickness of 200 nm.

FIGS. 7A and 7B show the surface state of the electrode layer for the case in which the IrO2 electrode layer is formed with a thickness of 300 nm while setting the sputtering power to 1 kW.

Referring to FIG. 7A, it can be seen that giant IrO2 crystals are formed on the electrode layer after the 25th substrate similarly to the case of FIG. 6, except that the degree of the abnormal crystal growth proceeds further to such a degree that development of crystal surfaces is recognized. As represented in FIG. 7B, such giant IrO2 crystals act as defects on the surface of the electrode layer . From FIG. 7B, it can be seen that the giant IrO2 crystal appears at the intermediate thickness of the IrO2 film, suggesting that the abnormal growth of the IrO2 crystal starts when the substrate temperature has reached a certain temperature as a result of continuation of the sputter deposition process of the IrO2 film for some time.

FIG. 8 shows the surface state of the IrO2 electrode layer for the case in which the electrode layer is formed by depositing an IrO2 film by a two-step process, first with a thickness of 100 nm while setting the sputtering power to 1 kW, and next for another 100 nm while increasing the sputtering power to 2 kW.

Referring to FIG. 8, the electrode layer has a surface in which fine IrO2 crystals, represented in FIG. 8 by white dots, are scattered uniformly, and the existence of giant crystals as explained with reference to FIGS. 7A and 7B is not recognized. In other words, formation of defects in the upper electrode layer is avoided when the deposition process includes an initial process in which the electrode layer is formed within the thickness of 100 nm while setting the sputtering power to be 1 kW or less. As long as the initial sputtering process is conducted with such a low sputtering power, formation of defects in the electrode layer does not occur even when the deposition of the IrO2 layer is continued thereon with a different sputtering condition. It should be noted that FIG. 8 shows the surface state of the substrate on which the 100th deposition has been made for the case in which 100 continuous deposition of the IrO2 electrode layer has been made on 100 substrates.

Generally, the formation of the giant crystals as represented in FIG. 6 or FIGS. 7A and 7B can be suppressed when the formation of the IrO2 electrode layer is conducted such that the IrO2 electrode layer has a thickness of 100 nm or less. In the experiments conducted by the inventor of the present invention, for example, no defect formation was observed in the 29th or later deposition experiments when the IrO2 electrode layer was formed with the thickness of 100 nm. When the IrO2 electrode layer was formed with the thickness of 50 nm, no defect formation was observed in the 30th or later deposition experiments. Further, the use of the low sputtering power is effective for avoiding the reduction of the underlying ferroelectric film and for realizing excellent electric property for the ferroelectric capacitor. In the example of FIG. 8, it should be noted that the IrO2 crystals have an average grain size of only 10-30 nm, while in the case of FIGS. 7A and 7B, the IrO2 crystals have an average grain size of 300-400 nm.

On the other hand, such a decrease of the sputtering power inevitably causes a decrease in the growth rate of the electrode layer as represented in FIG. 9, wherein it should be noted that FIG. 9 represents the relationship between the growth rate of the IrO2 electrode layer and the sputtering power. From FIG. 9, it can be seen that a growth rate of only 2-3 nm/sec is obtained when the sputtering power of 1 kW is used.

Meanwhile, the inventor of the present invention has discovered that the switching electric charge Qsw does not change substantially when an IrO2 electrode layer is formed on the ferroelectric film with low sputtering power such as 1 kW, followed by the sputtering process of another IrO2 electrode layer designated “A” as represented in FIG. 10 with an increased sputtering power or with an increased degree of reduction in the sputtering atmosphere.

Referring to FIG. 10, the IrO2 electrode layer is formed first by depositing an initial IrO2 film with a thickness of 100 nm while using the sputtering power of 1 kW, followed by depositing a further IrO2 film with a thickness of 100 nm while using the sputtering power of 2 kW or 4 kW. The deposition condition of the IrO2 films thus constituting the IrO2 electrode layer is summarized in TABLE IV below.

Thus, the present invention provides an efficient way of fabricating a ferroelectric capacitor characterized by an excellent electric property with improved yield, by first carrying out the deposition of the IrO2 electrode layer with a low sputtering power, and then carrying out the deposition with an increased sputtering power while using an oxidizing sputtering atmosphere.

Further, the inventor of the present invention has discovered that the leakage current of 1.50×10−4 A/cm2 for the ferroelectric capacitor in which the IrO2 electrode layer is formed with the sputtering power of 2 kW, is reduced to 2.0×10−5 A/cm2 by forming the IrO2 electrode layer with the sputtering power of 1 kW.

FIG. 11 shows the X-ray diffraction pattern of the IrO2 film obtained by a sputtering process conducted in an atmosphere containing oxygen under the condition of TABLE III while using the sputtering power of 1 kW.

Referring to FIG. 11, it can be seen that there is a distinct diffraction peak corresponding to the (110) surface of IrO2 at the diffraction angle 2θ of about 28°. Further, a diffraction peak corresponding to the (200) surface of IrO2 is observed at the diffraction angle of about 29°.

FIG. 12, on the other hand, shows the X-ray diffraction pattern of the IrO2 film deposited by a sputtering process conducted under the sputtering power of 2 kW.

Referring to FIG. 12, the IrO2 film formed according to such a process does not show the reflection of the (110) surface or the (200) surface observed in the case of FIG. 11 but only a strong reflection of Si is observed.

FIG. 13 shows the X-ray diffraction pattern of the IrO2 film formed according to the condition of TABLE IV explained before.

Referring to FIG. 13, it can be seen that the IrO2 film thus formed by the two-step process that uses the low sputtering power at the beginning and then increasing the sputtering power, shows an X-ray diffraction pattern similar to the one shown in FIG. 11 in that there are distinct diffraction peaks corresponding to the (110) surface and the (200) surface of IrO2.

FIGS. 14A-14E show the SIMS profile of various elements in the IrO2 electrode layer thus sputtered under various sputtering conditions, wherein FIG. 14A shows the distribution profile of the elements immediately after the deposition of the IrO2 electrode layer under the condition of TABLE III with the sputtering power of 1 kW, while FIG. 14B shows the distribution profile of the same elements after applying a thermal annealing process to the electrode layer .

Referring to FIG. 14A, it can be seen that the Pb concentration level is below the detection threshold in the state immediately after the deposition, while FIG. 14B shows that there occurs a substantial diffusion of Pb from the ferroelectric film into the IrO2 electrode layer when the thermal annealing process is applied at 650° C., and that there is formed a concentration profile of Pb as a result of the thermal annealing process such that the concentration level of Pb decreases gradually from the interface between the ferroelectric film and the IrO2 electrode layer toward the free surface of the layer .

On the other hand, FIG. 14C shows the distribution profile of the elements in the electrode layer immediately after the state in which the electrode layer is formed by a sputtering process conducted with the sputtering power of 2 kW, while FIG. 14D shows the distribution profile of the elements for the case a thermal annealing process is applied to the electrode layer of FIG. C.

Referring to FIG. 14C, it can be seen that the electrode layer contains Pb with a concentration level below the detection limit, while there appears a distribution profile of Pb in the electrode layer after the recovery annealing process as represented in FIG. 14D, such that the Pb concentration level is below the detection limit at the intermediate part of the layer while exceeds the detection limit in the vicinity of the free surface of the layer and the interface to the ferroelectric film .

Further, FIG. 14E shows the SIMS profile of the elements in the IrO2 electrode layer for the case the electrode layer is formed under the condition of TABLE IV while using a low sputtering power of 1 kW in the initial period of the sputter deposition process for depositing the IrO2 layer to the thickness of 100 nm and increasing the sputtering power to 2 kW after the initial period for depositing the IrO2 layer for another 100 nm.

Referring to FIG. 14E, it can be seen that the IrO2 electrode layer thus formed contains Pb with a generally uniform concentration level. This profile of Pb is maintained even when a recovery annealing process is applied to the ferroelectric film .

It should be noted that the IrO2 electrode layer of FIG. 14E thus formed according to the two-step process is in fact formed of a lower part contacting with the ferroelectric film and an upper part, wherein the lower part, formed under the strong oxidizing condition contains Ir primarily in oxidized state, while the upper part, formed under less strong oxidizing condition, contains a larger proportion of Ir in the metallic state as compared with the lower part.

In the present embodiment, it should be noted that the conductive oxide forming the electrode layer is by no means limited to IrO2 but other conductive oxides such as RhO2 or RuO2, or SrRuO3 may also be used. Further, it is possible to change the sputtering condition gradually in the process of TABLE IV for forming the first layer and the second layer.

[Second Embodiment]

FIGS. 15A-15R show the fabrication process of a semiconductor device according to a third embodiment of the present invention.

Referring to FIG. 15A, a p-type well A and an n-type well B are formed on a Si substrate , which may be any of the p-type or n-type, wherein the Si substrate is covered by a field oxide film defining an active region in each of the p-type well A and the n-type well B.

Next, a gate oxide film is formed on the active region of the p-type well A and also on the active region of the n-type well B, and a p-type polysilicon gate electrode A is formed on the gate oxide film in the p-type well A. Similarly, an n-type polysilicon gate electrode B is formed on the gate oxide film in correspondence to the n-type well B. In the illustrated example, polysilicon interconnection patterns C and D are formed further on the field oxide film similarly to the polysilicon gate electrodes A and B.

In the structure of FIG. 15A, there are formed n-type diffusion regions and in the active region of the p-type well A by introducing an n-type impurity element by an ion implantation process, while using the gate electrode A and the side wall insulation films thereon as a self-alignment mask. Similarly, p-type diffusion regions and are formed in the active region of the n-type well B by an ion implantation process of a p-type impurity element, while using the gate electrode B and the side wall insulation films thereon as a self-alignment mask.

The process so far is nothing but an ordinary CMOS process.

Next, in the step of FIG. 15B, an SiON film is deposited on the structure of FIG. 15A by a CVD process with a thickness of about 200 nm, and an SiO2 film is further deposited on the SiON film by a CVD process with a thickness of about 1000 nm.

Further, in the step of FIG. 15C, the SiO2 film is subjected to a CMP process while using the SiON film as a polishing stopper, and contact holes A-D are formed in the step of FIG. 15D in the SiO2 film thus planarized such that the diffusion regions , , and are exposed by the contact holes A, B, C and D. In the illustrated example, the SiO2 film is further formed with a contact hole E so as to expose the interconnection pattern C.

Next, in the step of FIG. 15E, a W layer is deposited on the structure of FIG. 15D so as to fill the contact holes A-E, wherein the W layer thus deposited is subjected to a CMP process in the step of FIG. 15F while using the SiO2 film as a stopper. As a result of the polishing process, there are formed W plugs A-E respectively in correspondence to the contact holes A-E as represented in FIG. F.

Next, in the step of FIG. 15G, an oxidization stopper film of SiN and an SiO2 film are deposited consecutively on the structure of FIG. 15F respectively with the thicknesses of 100 nm and 130 nm, followed by a thermal annealing process conducted in an N2 atmosphere at 650° C. for about 30 minutes. The thermal annealing process is conducted so as to thoroughly remove gases from the structure thus formed.

Next, in the step of FIG. 15H, a Ti film and a Pt film are deposited consecutively on the SiO2 film with respective thicknesses of 20 nm and 175 nm by a sputtering process, which may be conducted according to the condition represented in TABLE I. The Ti film and the Pt film thereon constitute a lower electrode layer of the ferroelectric capacitor to be formed.

After the deposition of the Ti film and the Pt film , a ferroelectric film of PZT or PLZT is sputter-deposited in the step of FIG. 15H under the condition of TABLE II, wherein the ferroelectric film may contain Ca or Sr.

Further, in the step of FIG. 15H, the ferroelectric film is subjected to a crystallization process by an RTA process conducted in an oxidizing atmosphere at the temperature of 750° C. for 20 seconds. During the RTA process, any oxygen defects formed in the ferroelectric film is compensated for. By using a large rate of temperature increase of 125° C./sec, the duration of the thermal annealing process is minimized.

Further, in the step of FIG. 15H, an IrO2 film is deposited on the ferroelectric film thus processed as an upper electrode layer with a thickness of about 200 nm by a sputtering process conducted according to the condition of TABLE IV.

Next, in the step of FIG. 15I, a resist pattern is formed on the upper electrode layer , followed by the patterning of the upper electrode layer by a dry etching process to form an upper electrode pattern A of IrO2 on the ferroelectric film . In the step of FIG. 15I, it should further be noted that the ferroelectric film is subjected, after the foregoing sputtering and patterning of the upper electrode pattern A, to a recovery annealing process conducted in an O2 atmosphere at 650° C. for 60 minutes so as to recover any damages caused in the ferroelectric film as a result of the foregoing sputtering and patterning processes.

Next, in the step of FIG. 15J, a resist pattern having a shape corresponding to the shape of the capacitor insulation film to be formed, is formed on the ferroelectric insulation film , and the ferroelectric insulation film is subjected to a dry etching process while using the foregoing resist pattern as a mask. As a result, a desired ferroelectric capacitor insulation film pattern A is formed on the underlying lower electrode layer . Further, an encapsulating layer B is formed on the lower electrode layer by a ferroelectric material having a composition substantially identical with that of the material constituting the ferroelectric film , by conducting a sputtering process with a thickness of about 20 nm. The encapsulating layer B thus deposited is then annealed by an RTA process in the O2 atmosphere at 700° C. for 60 seconds with a temperature profile of about 125° C./min. The encapsulating layer B thereby protects the ferroelectric capacitor insulation film pattern A from reduction.

Next, in the step of FIG. 15K, a resist pattern is formed on the lower electrode layer so as to cover the encapsulating layer B with a pattern corresponding to the lower electrode pattern to be formed. Further, by conducting a dry etching process on the foregoing encapsulating layer B and the underlying Pt and Ti films and underneath the encapsulating layer B by a dry etching process, a lower electrode pattern A is formed.

After the formation of the lower electrode pattern A, the resist pattern is removed in the step of FIG. 15K, and the damages that are introduced into the ferroelectric capacitor insulation film A during the dry etching process of the lower electrode pattern A are recovered by conducting a recovery annealing process in an O2 atmosphere at 650° C. for 60 minutes.

Next, in the step of FIG. 15L, an SiO2 film is deposited on the structure of FIG. 15K by a CVD process, typically with a thickness of about 200 nm, followed by a formation of an SOG film thereon, wherein the SOG film smoothes any sharp steps formed on the underlying SiO2 film . The SiO2 film and the SOG film form together an interlayer insulation film .

Next, in the step of FIG. 15M, contact holes A and B are formed in the interlayer insulation film so as to expose the upper electrode pattern A and the lower electrode pattern A respectively, and contact holes C and D are formed further in the step of FIG. 15N in the interlayer insulation film so as to expose the W plugs B and D respectively through the underlying SiO2 film and the SiN film . Further, in the step of FIG. 15M, a recovery annealing process is conducted, after the dry etching process for forming the contact holes A and B, in an O2 atmosphere at 550° C. for 60 minutes. As a result of the recovery annealing process, any damages introduced into the ferroelectric film patterns A and B during the dry etching process are eliminated.

Next, in the step of FIG. 150, a local interconnection pattern A is formed by a TiN film such that the local interconnection pattern A connects the contact hole A and the contact hole C electrically. Further, a similar local interconnection pattern B and C are formed on the contact holes B and C.

Next, in the step of FIG. 15P, an SiO2 film is formed on the structure of FIG. 150, and contact holes A, B and C are formed in the SiO2 film in the step of FIG. 15Q so as to expose the W plug A, the local interconnection pattern B and the W plug C, respectively.

Further, in the step of FIG. 15R, electrodes A, B and C are formed respectively in correspondence to the contact holes A, B and C.

Further, the process of forming the interlayer insulation film and the interconnection patterns may be repeated as desired, to form a multilayer interconnection structure.

According to the present embodiment, the problem of defect formation in the upper electrode A is successfully eliminated while maintaining a practical deposition rate when forming the IrO2 film , by conducting the sputtering process in two steps, first with a lower sputtering power and then with an increased sputtering power. Further, such a two-step sputtering process of the IrO2 layer successfully prevents deterioration of the electric properties of the ferroelectric capacitor insulation film A.

Further, the present invention is not limited to the embodiments described heretofore, but various variations and modifications may be made without departing from the scope of the present invention.

Other objects and further features of the present invention will become apparent from the following detailed description when read in conjunction with the attached drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a circuit diagram showing the construction of a conventional ferroelectric random access memory device;

FIG. 2 is a cross-sectional diagram showing the construction of a ferroelectric capacitor according to a first embodiment of the present invention;

FIG. 3 is a diagram showing the relationship between the reflectance of an IrO2 film formed by a reactive sputtering process and a gas flow-rate in relation to the first embodiment of the present invention;

FIG. 4 is a diagram showing the relationship between the reflectance of an IrO2 film formed by a reactive sputtering process and a sputtering power in relation to the first embodiment of the present invention;

FIG. 5 is a diagram showing the relationship between the switching electric charge of the ferroelectric capacitor of FIG. 2 and a sputtering power;

FIG. 6 is a diagram showing an example of defects formed in an IrO2 film deposited according to a conventional process;

FIGS. 7A and 7B are diagrams showing further examples of the defects formed in an IrO2 film deposited according to a conventional process;

FIG. 8 is a diagram showing the surface state of an IrO2 film formed according to the process of the present invention;

FIG. 9 is a diagram showing the relationship between the deposition rate of the IrO2 film formed according to the process of the present invention and a sputtering power;

FIG. 10 is a diagram showing the electric property of the ferroelectric capacitor formed according to the process of the present invention;

FIG. 11 is a diagram showing the X-ray diffraction pattern of an IrO2 film formed with a sputtering power of 1 kW;

FIG. 12 is a diagram showing the X-ray diffraction pattern of an IrO2 film formed with a sputtering power of 2 kW;

FIG. 13 is a diagram showing the X-ray diffraction pattern of an IrO2 film formed by a two-step process that uses a sputtering power of 1 kW at the beginning and then increasing to 2 kW;

FIGS. 14A-14E are diagrams showing the SIMS profile of various elements in an IrO2 film formed under various sputtering conditions; and

FIGS. 15A-15R are diagrams showing the fabrication process of a ferroelectric random access memory according to a second embodiment of the present invention.

CROSS-REFERENCE TO RELATED APPLICATION

This application is a Divisional of prior application Ser. No. 09/694,303 filed Oct. 24, 2000 now U.S. Pat. No. 6,531,726, which is hereby incorporated by reference.

CLAIMS

1. A method of fabricating a ferroelectric capacitor, comprising the steps of: forming a lower electrode; forming a ferroelectric film on said lower electrode; and forming an upper electrode on said ferroelectric film, said step of forming said upper electrode comprising a first reactive sputtering process of a conductive oxide film and a second reactive sputtering process of said conductive oxide film conducted after said first reactive sputtering process, said first and second reactive sputtering process being conducted by using a target of a metal element constituting said conductive oxide film, said first reactive sputtering process being conducted under a first, oxidizing condition such that oxidation of said metal element takes place, said second reactive sputtering process being conducted under a second, less oxidizing condition.

2. A method as claimed in claim 1, wherein said first reactive sputtering process is conducted under a sputtering power of about 1 kW or less.

3. A method as claimed in claim 1, wherein said second reactive sputtering process is conducted with a sputtering power of about 2 kW or more.

4. A method as claimed in claim 1, wherein said first reactive sputtering process and second reactive sputtering process are conducted consecutively while changing a sputtering condition continuously from said first condition to said second condition.

5. A method as claimed in claim 1, wherein said first reactive sputtering process is conducted such that said conductive oxide film is formed with a thickness of about 100 nm or less.

6. A method as claimed in claim 1, wherein said conductive oxide film is selected from the group consisting of IrO2, RhO2, RuO2 and SrRuO3.

7. A method of fabricating a ferroelectric capacitor, comprising the steps of: forming a lower electrode; forming a ferroelectric film on said lower electrode; and forming an upper electrode on said ferroelectric film, said step of forming said upper electrode comprising a reactive sputtering process of a conductive oxide film that uses a target of a metal element constituting said conductive oxide film, said reactive sputtering process being conducted under an oxidizing condition such that oxidation of said metal element takes place, said sputtering process being conducted while using a sputtering power of about 1 kW or less.

8. A method as claimed in claim 7, wherein said sputtering process is conducted such that said conductive oxide film has a thickness of about 100 nm or less.

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