Methods of fabricating buried digit lines

ABSTRACT

A method for electrically linking the contacts of a semiconductor device to their corresponding digit lines includes disposing a quantity of mask material into a trench through which the contact is exposed. The mask also abuts a connect region of a conductive element of a corresponding conductive line and, therefore, protrudes somewhat over a surface of the semiconductor device. A layer of insulative material is formed over the semiconductor device with the mask exposed therethrough. The mask is then removed, leaving open cavities, including the trench and a strap region continuous with both the trench and a connect region of the corresponding conductive line. Conductive material is introduced into each open cavity to define conductive plugs or studs and conductive straps that are electrically isolated from one another. Semiconductor devices including features that have been fabricated in accordance with the method are also within the scope of the present invention.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE INVENTION

With reference to FIGS. 1A and 1B, a semiconductor memory device according to the present invention is illustrated. Semiconductor memory device , which is also referred to herein as a semiconductor device, includes a substrate including an array of conductively doped regions therein. Preferably, substrate comprises a p-type semiconductor material. Doped regions preferably comprise an n-type semiconductor material and may, therefore, also be referred to herein as n-wells. Word lines extend across a rate in a substantially mutually parallel relationship to one another. The regions of substrate disposed between adjacent word lines are referred to as bit contact regions .

Bit contact regions that are doped (i.e., comprise doped regions of substrate ) are referred to as bit contacts . Bit contact regions or the bit contacts thereof are exposed to a surface of semiconductor memory device by means of a trench aligned between adjacent word lines . Sidewall spacers , which are disposed adjacent word lines , electrically isolate the conductive elements of word lines from the adjacent trench . A plug of conductive material disposed within trench and an adjacent strap of conductive material provide an electrically conductive link between bit contact and a corresponding digit line that extends across semiconductor memory device substantially perpendicularly to word lines .

Each digit line preferably includes a conductive element , an insulative cap disposed over conductive element , and a sidewall spacer disposed laterally adjacent conductive element and opposite strap . The conductive element of each digit line preferably includes a metal silicide layer and a conductive layer disposed over metal silicide layer . Conductive layer preferably comprises polysilicon.

Preferably, digit lines have a width of less than about 0.25 microns and, more preferably, of at most about 0.18 microns. Adjacent digit lines are preferably spaced less than about 0.30 microns apart from one another and, more preferably, at most about 0.22 microns apart from one another. Thus, digit lines preferably have a pitch of less than about 0.55 microns and, more preferably, of at most about 0.40 microns.

Turning now to FIGS. 2-16, a method is illustrated by which digit lines (see FIGS. 1A and 1B) of a desired thickness and pitch may be fabricated upon and in communication with corresponding bit contacts of a semiconductor memory device .

With reference to FIG. 2, a semiconductor memory device , which includes a trench through which a bit contact region is exposed, is illustrated. The conductive elements of the word lines of semiconductor memory device that are adjacent bit contact region are exposed to trench . Trench may be defined by known processes, such as mask and etch techniques, in order to expose bit contact region .

As shown in FIG. 3, if bit contact region of substrate has not been doped, bit contact region may be doped by known processes, such as by implanting bit contact region with arsenic. Alternatively, bit contact region may be doped after digit lines (see FIGS. 1A and 1B) have been fabricated and prior to fabricating plug or strap (see FIGS. A and B).

As illustrated in FIG. 4, any portions of the conductive elements of word lines that are exposed to trench may be electrically isolated from trench by means of sidewall spacers . Of course, sidewall spacers may be fabricated as known in the art, such as by exposing the conductive material of word lines to an oxidizing temperature, or by disposing a known oxidizing material in contact therewith, or by disposing an insulative material adjacent the conductive material of word lines and patterning the insulative material to define sidewall spacers therefrom.

Referring to FIG. 5, a layer of silicon nitride may be disposed over a surface of semiconductor memory device . Preferably layer of silicon nitride is disposed substantially over the surface of semiconductor memory device , including the bit contacts thereof. Layer may be fabricated as known in the art, such as by chemical vapor depositing (“CVD”) silicon nitride over the surface on semiconductor memory device . Such a silicon nitride layer may subsequently be employed as an etch stop.

Turning to FIG. 6, one or more layers of digit line material or materials may be disposed over the surface of semiconductor memory device . As illustrated, a first digit line layer may comprise a metal silicide. Preferably, first digit line layer comprises a refractory metal silicide, such as titanium silicide, tantalum silicide, cobalt silicide, or tungsten silicide. First digit line layer may be fabricated as known in the art, such as by chemical vapor deposition or by fabricating adjacent layers of silicon and metal and annealing these layers to one another.

A second digit line layer may be disposed over first digit line layer . Second digit layer preferably comprises an electrically conductive material, such as a metal or polysilicon. Second digit line layer may be fabricated, as known in the art, such as by chemical vapor deposition or physical vapor deposition (“PVD”).

With reference to FIG. 7, an insulative layer may be disposed over the layer or layers of digit line material. As shown, insulative layer is disposed over second digit line layer . Insulative layer may be fabricated as known in the art, such as by oxidizing an underlying layer or of digit line material or by disposing an electrically insulative material over layer of digit line material by chemical vapor deposition, spin-on-glass (“SOG”), or other know process. As digit lines are defined through the layer or layers of digit line material, insulative layer may be employed as an insulative cap (see FIGS. 1A and 1B) over each of the digit lines .

Referring now to FIGS. 8-8B, a first mask may be disposed over the uppermost layer of digit line material. As shown in FIG. 8A, mask includes a plurality of mutually paralled apertures that are alignable over trenches and bit contacts . As illustrated, first mask shields elongated areas of semiconductor memory device , over which digit lines are to be defined. As shown in FIG. 8B, first mask also preferably shields the periphery of each die of a wafer that includes a plurality of dice . Although first mask may be fabricated by any known process, the use of photomask technology is preferred. When a photomask is employed as first mask , a photoresist may be disposed over a surface of semiconductor memory device by known processes, such as by spinning the photoresist onto semiconductor memory device , and the layer of photoresist exposed and developed, as known in the art.

With reference to FIGS. 9 and 9A, digit lines may be defined through first mask . Known patterning processes may be employed to define digit lines and their overlying insulative caps . Preferably, one or more isotropic etchants are employed to remove the materials of insulative layer , second digit line layer , and first digit line layer either directly or indirectly (i.e., through apertures formed through an overlying layer) through apertures of first mask . With reference to FIG. 10, the underlying layer of silicon nitride may also be removed by known processes, such as by the use of an isotropic etchant.

With reference to FIG. 9B, if a first mask that shielded the peripheries of dice (see FIG. 8B) was employed, a second mask may be employed to remove any regions of insulative layer , second digit line layer , first digit line layer , or layer of silicon nitride that remain at the peripheries of dice . Preferably, second mask substantially shields digit lines and other features of semiconductor memory device , which are collectively referred to herein as a central region of the semiconductor memory device, and includes apertures that expose the peripheries of dice . Second mask may be disposed upon semiconductor memory device and defined, as known in the art, such as by the use of photomask techniques. Any digit line materials, insulative materials, or silicon nitride that remain on the peripheries of dice may be removed either directly or indirectly through second mask by known processes, such as by the use of etchants. The masks and may each be removed from semiconductor memory device by known processes.

Referring to FIG. 10, upon removing layer of silicon nitride, bit contact regions are again exposed through trenches . Portions of sidewall spacers may also be removed as silicon nitride layer is removed. Accordingly, it may be necessary to re-isolate the conductive elements of word lines from their corresponding trench . Again, known processes may be employed to fabricate sidewall spacers adjacent the conductive elements of word lines .

Since bit contact regions of substrate are again exposed through their corresponding trench , bit contact regions may be conductively doped, as known in the art, to form bit contacts if such doping was not previously performed.

Referring now to FIG. 11, another mask may be disposed over semiconductor memory device . Preferably, mask comprises a photomask, which may be defined by known processes, such as by disposing a photoresist over semiconductor memory device and exposing and developing selected regions of the photoresist. Mask preferably substantially fills each of the trenches of semiconductor memory device and, thereby, shields bit contacts . Mask also extends laterally over a strap region of the semiconductor memory device . Each strap region is disposed between a trench and its corresponding digit line . Thus, mask may protrude from trench and somewhat from the surface of semiconductor memory device . Preferably, mask contacts an exposed, electrically conductive lateral edge portion of the adjacent digit line . Mask is preferably hard-baked, as known in the art, to facilitate the fabrication of structures (i.e., conductive plugs and straps) having the desired dimensions and configurations.

Turning to FIG. 12, another layer of insulative material may be disposed over semiconductor memory device . Preferably, mask is exposed through layer of insulative material. Insulative material layer preferably has a substantially planar surface. Accordingly, insulative layer may be fabricated by known tetraethylorthosilicate (“TEOS”) wet dip processes. Alternatively, layer of insulative material may be deposited over semiconductor memory device by known processes, such as by chemical vapor deposition or spin-on processes. Mask may then be exposed through insulative material layer by known processes, such as by planarizing insulative material layer (e.g., by chemical-mechanical planarization (“CMP”)) or by employing a blanket isotropic etch-back. Insulative material layer preferably insulates the exposed lateral edges of digit lines , and may cover digit lines .

With reference to FIG. 13, mask may be removed from semiconductor memory device by known processes, such as by the use of solvents or heat, and semiconductor memory device washed. Upon removing mask from semiconductor memory device , cavities , which are defined by trenches , insulative material layer , and digit lines , are exposed.

As shown in FIG. 14, upon disposing a layer of conductive material over semiconductor memory device , cavities are preferably substantially filled with the conductive material. Thus, the conductive material of layer establishes an electrically conductive link between each bit contact and its corresponding digit line . Conductive material of layer may be fabricated by known techniques, such as by physical vapor deposition (e.g., sputtering) or by chemical vapor deposition. Preferably, polysilicon is employed as the conductive material of layer .

Referring to FIG. 15, the uppermost portions of conductive material layer are preferably removed so as to substantially expose insulative material layer through conductive material layer . Accordingly, the remaining portions of conductive material layer are substantially confined within cavities and define conductive plugs and straps . The uppermost portions of layer may be removed by known processes, such as by employing blanket isotropic etch-back techniques. Alternatively, another mask could be disposed over the semiconductor device and the plugs and straps defined through apertures thereof.

With reference to FIG. 16, yet another mask may be disposed over semiconductor memory device . Mask preferably shields the portions of layer of conductive material that are disposed within cavities . Mask may also shield digit lines . The remaining regions of semiconductor memory device are preferably exposed through mask . Known processes may be employed to fabricate mask , such as the use of photomask techniques.

The regions of semiconductor memory device that are exposed through mask are preferably exposed to an anisotropic etchant in order to further define plugs and straps and to remove any stringers of the conductive materials employed in layers , , and that may remain in these exposed regions. Preferably, an isotropic etchant is then employed to remove any remaining conductive materials that are exposed through mask . Accordingly, the use of both an anisotropic and an isotropic etchant is useful to substantially remove any stringers that may extend from or between plugs , straps , or digit lines and that may cause electrical shorts in semiconductor memory device , while facilitating the fabrication of digit lines having a thickness of less than about 0.25 microns and a pitch of less than about 0.55 microns.

An insulative layer may then be disposed over plugs and straps by known processes. Other structures may also be fabricated over plugs , straps , and their corresponding digit lines , as known in the art.

Although the foregoing description contains many specifics and examples, these should not be construed as limiting the scope of the present invention, but merely as providing illustrations of some of the presently preferred embodiments. Similarly, other embodiments of the invention may be devised which do not depart from the spirit or scope of the present invention. The scope of this invention is, therefore, indicated and limited only by the appended claims and their legal equivalents, rather than by the foregoing description. All additions, deletions and modifications to the invention as disclosed herein and which fall within the meaning of the claims are to be embraced within their scope.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

FIG. 1A is a schematic cross-sectional representation of a semiconductor memory device according to the present invention and fabricated in accordance with the method of the present invention;

FIG. 1B is a schematic cross-sectional representation of the semiconductor memory device of FIG. 1A, taken along the plane of line B-B, which extends perpendicularly through the plane of the page; and

FIGS. 2-16 are schematic representations that illustrate an embodiment of the method of the present invention.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 10/032,730, filed Dec. 28, 2001, now U.S. Pat. No. 6,555,463 issued Apr. 29, 2003, which is a continuation of application Ser. No. 09/650,797, filed Aug. 30, 2000, now U.S. Pat. No. 6,372,629, issued Apr. 16, 2002, which is a continuation of application Ser. No. 09/388,769, filed Sep. 2, 1999, now U.S. Pat. No. 6,180,508, issued Jan. 30, 2001.

CLAIMS

1. A method for interconnecting a contact and a corresponding conductive line of a semiconductor device structure, comprising: forming a mask to substantially fill a trench through which the contact is exposed and to contact the corresponding conductive line; forming an insulative structure at least laterally adjacent to the mask; removing at least a portion of the mask from the trench so as to expose the contact; and forming an interconnect between the contact and the corresponding conductive line.

2. The method of claim 1, wherein forming the mask comprises forming the mask so as to contact an active-device region of the semiconductor device structure exposed through the trench.

3. The method of claim 1, wherein forming the mask comprises forming the mask so as to contact a conductive structure that communicates with an active-device region of the semiconductor device structure and that is exposed through the trench.

4. The method of claim 1, wherein forming the mask comprises substantially filling the trench with a mask comprising a photoresist.

5. The method of claim 4, further comprising substantially curing the photoresist.

6. The method of claim 5, wherein substantially curing comprises selectively exposing and developing selected regions of the photoresist.

7. The method of claim 5, further comprising hard-baking the photoresist.

8. The method of claim 1, wherein forming the insulative structure comprises forming an insulative structure comprising tetraethylorthosilicate.

9. The method of claim 1, wherein forming the insulative structure comprises chemical vapor depositing at least insulative material onto the semiconductor device structure.

10. The method of claim 9, further comprising exposing the mask through the insulative material.

11. The method of claim 10, wherein exposing the mask comprises planarizing a material of the insulative structure.

12. The method of claim 11, wherein planarizing comprises at least abrasively polishing the material.

13. The method of claim 10, wherein exposing comprises removing at least portions of the insulative structure overlying the mask.

14. The method of claim 1, wherein forming the interconnect includes depositing conductive material at least between the contact and the corresponding conductive line.

15. The method of claim 14, wherein forming the interconnect further includes removing conductive material from other areas of the semiconductor device structure.

16. The method of claim 15, wherein removing conductive material comprises electrically isolating contacts of the semiconductor device structure from one another.

17. The method of claim 1, wherein forming the interconnect comprises forming a conductive strap between the contact and its corresponding conductive line.

18. A method for electrically interconnecting at least one active device region and a corresponding conductive line of a semiconductor device structure, comprising: forming a mask to substantially fill at least one trench to which the at least one active device region is exposed and to contact the corresponding conductive line; and forming an insulative structure at least laterally adjacent to the mask.

19. The method of claim 18, further comprising removing at least portions of the mask from the at least one trench following forming the insulative structure so as to expose at least a portion of the at least active device region exposed thereto.

20. The method of claim 19, further comprising forming an interconnect in communication with both the at least one active device region and the corresponding conductive line.

21. The method of claim 20, wherein said forming the interconnect includes introducing conductive material into the at least one trench and in communication with the corresponding conductive line.

22. The method of claim 21, wherein forming the interconnect further includes patterning the conductive material to form a conductive strap that extends between the at least one active device region and the corresponding conductive line.

COPYRIGHT

User acknowledges that Fairview Research and its third party providers retain all right, title and interest in and to this xml under applicable copyright laws. User acquires no ownership rights to this xml including but not limited to its format. User hereby accepts the terms and conditions of the License Agreement.