Method for fabricating a memory chip

ABSTRACT

An ovonic phase-change semiconductor memory device having a reduced area of contact between electrodes of chalcogenide memories, and methods of forming the same. Such memory devices are formed by forming a tip protruding from a lower surface of a lower electrode element. An insulative material is applied over the lower electrode such that an upper surface of the tip is exposed. A chalcogenide material and an upper electrode are either formed atop the tip, or the tip is etched into the insulative material and the chalcogenide material and upper electrode are deposited within the recess. This allows the memory cells to be made smaller and allows the overall power requirements for the memory cell to be minimized.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE INVENTION

A method of fabricating a small area of contact between electrodes of chalcogenide memories is presented that provides an area of contact with the lower electrode by the upper electrode, via the chalcogenide material, that is smaller than that presently producible using conventional photolithographic techniques. In particular, the preferred embodiment of the present invention provides a method of fabricating electrodes for chalcogenide memories in which an area of contact of the lower electrode with the upper electrode is minimized by forming a tip or protrusion extending from a surface of the lower electrode. In this manner, the lower electrode having a minimum area of contact as small as π×(0.05 μm)2 is obtained. An insulative material is applied over the lower electrode in a manner such that an upper surface of the tip is exposed, while the surrounding surface of the lower electrode remains covered. The chalcogenide material and upper electrode are either formed atop the tip, or the tip is etched to form a recess in the insulative material and the chalcogenide material and upper electrode are deposited therein as successive layers. The present invention provides enhanced control of the current passing through the resulting chalcogenide memory, and thus reduces the total current and energy input required to the chalcogenide active region in operation. The total current passing through the chalcogenide active region is two milliamps (mA). Thus, the current density required by the preferred embodiment is 1×106 A/cm2 to 1×107 A/cm2. Furthermore, the structure of the preferred embodiment allows the memory cells to be made smaller than that in the prior art and thus facilitates the production of denser memory arrays, and allows the overall power requirements for memory cells to be minimized.

Reference will now be made in detail to the presently preferred embodiment of the invention, an example of which is illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or equivalent elements.

It should be understood that the illustrations in FIGS. 1-23 do not comprise actual views of any particular semiconductor device, but merely are idealized representations which are employed to more clearly and fully depict the process and structure of the invention than would otherwise be possible.

Turning to the drawings and referring to FIGS. 1 to , a method for fabricating a small area of contact between an upper and lower electrode for chalcogenide memories will now be described. A layer of conductive material , preferably polysilicon, is deposited onto a substrate using conventional thin film deposition methods such as, for example, chemical vapor deposition (CVD), as illustrated in FIG. . The conductive material layer may have a substantially uniform thickness ranging from about 5000 to 7000 Angstroms, and preferably will have a substantially uniform thickness of approximately 6500 Angstroms. The substrate may also comprise a conductive material such as, for example, silicon, tin, carbon, WSix, or tungsten, and preferably will comprise silicon. The substrate will further preferably comprise a lower electrode grid (not shown) used for accessing an array of chalcogenide memories.

A layer of silicon oxide is deposited onto the substrate , preferably by CVD, and will preferably have a thickness of about 500 Angstroms. A layer of resist material is applied onto the silicon oxide layer , as illustrated in FIG. . The resist material layer will preferably have a substantially uniform thickness of approximately 15,000 Angstroms.

A contact pattern is then etched in the resist material layer and the silicon oxide layer using conventional masking, exposing, etching, and photoresist stripping techniques, as shown in FIG. . The contact pattern may be defined from the resist material layer and silicon oxide layer , for example, as a generally rectangular block as shown in FIG. (), or as a substantially circular block as shown in FIG. (). The contact pattern is preferably formed using a conventional contact hole mask, resulting in the substantially circular block shown in FIG. (). The minimum lateral dimension of the contact pattern preferably will be approximately 0.4 μm. The contact pattern (see FIG. 3) includes a generally horizontal bottom surface common to the conductive material layer , and generally vertical side walls at its outer periphery.

After the contact pattern has been patterned in the silicon oxide layer , the resist material layer is then removed using conventional stripping techniques, as shown in FIG. . Thus, the silicon oxide layer remains as the contact pattern . The silicon oxide layer contact pattern is used as a masking layer when the conductive material layer is subsequently etched.

The portion of the conductive material layer not covered by silicon oxide layer pattern is etched using wet etch or dry plasma etching techniques. The portions of conductive material layer beneath silicon oxide layer pattern being undercut to form a frustoconical shaped tip or protrusion above the remaining exposed surface of the conductive material layer , as shown in FIG. . The frustoconical tip preferably has a minimum frustum lateral dimension D of approximately 0.1 μm. The base of the tip preferably will have a base minimum lateral dimension of approximately 0.4 μm, i.e., the same dimension as the lateral dimension of the contact pattern . The tip will preferably have a height of approximately 2000 Angstroms. The removal of the silicon oxide layer is accomplished using conventional wet etch techniques, as shown in FIG. . The contact pattern thus provides a means for defining the area of contact of the base of the frustoconical tip of the conductive material layer of about 0.00785 μm2 [π×(0.05 μm)2]. Although the above dimensions are given as “preferred”, it is understood that a goal of the present invention is to form the tip as small as possible while maintaining uniformity and dimensional control.

A layer of insulative material is deposited onto the conductive material layer , including the tip , using conventional thin film deposition methods such as, for example, CVD, to isolate the conductive material layer , including the tip , as illustrated in FIG. . The insulative material layer may have a substantially uniform thickness of approximately 2000 to 5000 Angstroms, and preferably will have a substantially uniform thickness of approximately 2000 Angstroms, i.e., the same thickness as the height of the tip . The insulative material layer may comprise silicon oxide or silicon nitride, and preferably will comprise silicon oxide.

The insulative material layer is then preferably planarized using a conventional abrasive technique such as a chemical mechanical planarization (CMP) process, as illustrated in FIG. 9, to form an intermediate structure . The CMP process is performed to expose a top surface of the tip formed on the conductive material layer that may also be referred to as the lower electrode.

The chalcogenide memory cell is then formed by incorporating the tip of the conductive material layer using conventional semiconductor processing techniques such as, for example, thin-film deposition, masking, and etching processes. As shown in FIG. 15, the chalcogenide memory cell preferably includes a base layer of chalcogenide material , an interlayer dielectric (ILD) layer , an optional conductive barrier layer , a second layer of conductive material serving as an upper electrode, and an upper conductive grid interconnect .

The chalcogenide material layer may be deposited using conventional thin film deposition methods, as shown in FIG. . The chalcogenide material layer preferably is approximately 500 Angstroms thick. Typical chalcogenide compositions for these memory cells are alloys of tellurium (Te), germanium (Ge), and antimony (Sb). Such alloys include average concentrations of Te in the amorphous state well below 70%, typically below about 60% and ranging in general from as low as about 23% up to about 56% Te, and most preferably to about 48% to 56% Te; concentrations of Ge typically above about 15% and preferably range from a low of about 17% to about 44% on average, and remain generally below 50% Ge, with the remainder of the principal constituent elements in this class being Sb. The percentages are atomic percentages which total 100% of the atoms of the constituent elements. In a particularly preferred embodiment, the chalcogenide compositions for these memory cells comprise a Te concentration of 56%, a Ge concentration of 22%, and an Sb concentration of 22%. The materials are typically characterized as TeaGebSb100−(a+b), where a is equal to or less than about 70% and preferably between about 40% and about 60%, b is above about 15% and less than 50%, and preferably between about 17% and 44%, and the remainder is Sb.

An optional conductive barrier layer may be provided over the chalcogenide material layer using conventional thin film deposition techniques, as shown in FIG. . The second conductive material layer is deposited over the optional conductive barrier layer using conventional deposition techniques, as further shown in FIG. . The optional conductive barrier layer is disposed between the chalcogenide material layer and the second conductive material layer when these layers are made of such materials which will diffuse into one another. The optional conductive barrier layer prevents such diffusion. Although carbon is a preferred material to form the optional barrier layer , numerous conductive materials and metals known in the art may be used.

The second conductive material layer provides an upper electrode for the chalcogenide memory cell. The second conductive material layer is preferably titanium nitride (TiN), but may comprise TiN or carbon, and has a thickness of approximately 500 Angstroms. Layers ,, and are subsequently etched using conventional masking and etching techniques, as shown in FIG. .

As shown in FIG. 13, the ILD layer is then applied using conventional thin film deposition techniques. The ILD layer preferably is approximately 3500 Angstroms thick, and comprises silicon oxide. The ILD layer is then selectively etched, as shown in FIG. 14, using conventional masking and etching processes, to provide access to the surface of the second conductive material layer defining the upper electrode by an upper conductive grid interconnect . The upper conductive grid interconnect may be formed by first applying a blanket deposition of conductive material using conventional thin film deposition processes and then by etching the conductive material to form the upper conductive grid interconnect extending above the surface of the ILD layer , as shown in FIG. . The upper conductive grid interconnect material may comprise materials such as, for example, Ti, TiN, or aluminum, and preferably will comprise aluminum.

In an alternative embodiment shown in FIGS. 16-21, an intermediate structure is fabricated by substantially the same method as described above and illustrated in FIGS. 1-9. Elements common to both FIGS. 1-15 and FIGS. 16-21 retain the same numeric designation. FIG. 16 illustrates an intermediate structure (analogous to FIG. 9) after planarization of the layer of the insulative material using a conventional CMP process. As shown in FIG. 17, an etch mask is applied over the insulative material layer to expose the top surface of the tip . The tip is then etched to form a recess in insulative material layer , as shown in FIG. . Preferably, the recess is etched without a mask if an appropriate etchant selective between the insulative material layer and the conductive material layer of the tip is used, such as wet etching using NH4OH/KOH or dry etching using SF6.

As shown in FIG. 19, the chalcogenide material layer is applied over the insulative material layer such that a portion is deposited as a layer of chalcogenide material in the recess . A second conductive material layer is deposited over the chalcogenide material layer such that a portion extends into recess to form the second conductive material layer over the chalcogenide material layer , as shown in FIG. . The second conductive material layer and chalcogenide material layer over the insulative material layer is then removed, preferably by a CMP process, to form a structure , as shown in FIG. . An upper conductive grid interconnect may then be formed by conventional techniques to contact the second conductive material layer , such as shown in the FIG. .

It is, of course, understood that the chalcogenide material layer on the upper surface of the insulative material layer can be removed, such as by CMP, prior to depositing the second conductive material layer . Furthermore, a carbon layer may be interposed between the chalcogenide material layer and the second conductive material layer .

In a particularly preferred embodiment, the methods described above are utilized to form an array of chalcogenide memory cells that are addressable by an X-Y grid of upper and lower conductors, i.e., electrodes, as shown in FIG. . In the particularly preferred embodiment, diodes are further provided in series with the chalcogenide memory cells to permit read/write operations from/to individual chalcogenide memory cells , as will be recognized by persons of ordinary skill in the art. Thus, the chalcogenide memory cells can be utilized in a memory chip which interacts with a CPU (central processing unit) within a computer , as schematically illustrated in FIG. .

It is also understood that if a conductive barrier layer is required between the chalcogenide material layer and the second conductive material layer , a structure shown in FIG. 24 may be formed.

The intermediate structure (FIGS. 9 and 16) may also be formed by an alternative method shown in FIGS. 25-32. Elements common to both FIGS. 1-9 and FIGS. 25-32 retain the same numeric designation. A layer of conductive material is deposited onto a substrate , as illustrated in FIG. 25. A layer of silicon oxide is deposited onto the substrate and a layer of resist material is applied onto the silicon oxide layer , as illustrated in FIG. 26. A contact pattern is then etched in the resist material layer and the silicon oxide layer , as shown in FIG. .

After the contact pattern has been patterned in the silicon oxide layer , the resist material layer is then removed using conventional stripping techniques, as shown in FIG. . Thus, the silicon oxide layer remains as the contact pattern . The silicon oxide layer contact pattern is used as a masking layer when the conductive material layer is subsequently etched.

The portion of the conductive material layer not covered by silicon oxide layer pattern is etched using wet etch or dry plasma etching techniques. The portions of conductive material layer beneath silicon oxide pattern being undercut to form a sharp tip above the remaining exposed surface of the conductive material layer , as shown in FIG. . The silicon oxide pattern is then removed, as shown in FIG. 30. A layer of insulative material is deposited onto the conductive material layer to a level above the sharp tip , as illustrated in FIG. . The insulative material layer is then preferably planarized using a conventional abrasive technique such as a chemical mechanical planarization (CMP) process, as illustrated in FIG. 32, to form the intermediate structure . The CMP process is performed to level and expose a top surface of the sharp tip formed on the conductive material layer . This method allows for greater control of a surface area of top surface of the sharp tip by controlling the depth of the planarization. Once the intermediate structure , the chalcogenide memory cell may then be formed using the methods described above and shown in FIGS. 10-15 FIGS. 16-21.

The present invention includes the simultaneous fabrication of a plurality of tips on the lower electrode, i.e., the conductive material layer , such that a plurality of chalcogenide memory cells comprising an array may be created. The drawings show only a single tip for ease of illustration of the present invention. Furthermore, while a range of materials may be utilized for each layer, the particular materials selected for each layer must be selected to provide proper selectivity during the various etching processes as will be recognized by persons of ordinary skill in the art.

Having thus described in detail preferred embodiments of the present invention, it is to be understood that the invention defined by the appended claims is not to be limited by particular details set forth in the above description, as many apparent variations thereof are possible without departing from the spirit or scope thereof

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

While the specification concludes with claims particularly pointing out and distinctly claiming that which is regarded as the present invention, the advantages of this invention can be more readily ascertained from the following description of the invention when read in conjunction with the accompanying drawings in which:

FIG. 1 is a side cross-sectional view of the deposition of a layer of polysilicon onto a substrate of titanium nitride in accordance with a preferred embodiment of the present invention;

FIG. 2 is a side cross-sectional view of the deposition of a layer of silicon oxide and a layer of resist material onto the layer of polysilicon;

FIG. 3 is a side cross-sectional view of a contact pattern that is etched in the layer of resist material and the silicon oxide layer using etching, masking, and photoresist stripping techniques;

FIG. () is a top plan view of a generally rectangular contact pattern formed from the resist material and silicon oxide layers;

FIG. () is a top plan view of a generally circular contact pattern formed from the resist material and silicon oxide layers,

FIG. 5 is a side cross-sectional view of the device after the resist material layer has been stripped away using strip etching techniques;

FIG. 6 is a side cross-sectional view of a portion of the layer of polysilicon material not covered by the silicon oxide layer pattern that is etched using conventional undercut isotropic etching techniques to form a frustoconical shaped tip in the layer of polysilicon material;

FIG. 7 is a side cross-sectional view of the device after the contact pattern has been removed using conventional wet etch techniques;

FIG. 8 is a side cross-sectional view of the depositing of a layer of insulative material onto the layer of polysilicon material, including the tip, using conventional thin film deposition methods to isolate the layer of polysilicon material, including the tip;

FIG. 9 is a side cross-sectional view of planarization of the layer of insulative material using a conventional chemical mechanical planarization (CMP) process;

FIG. 10 is a side cross-sectional view of a chalcogenide material layer that is deposited using conventional thin film deposition methods;

FIG. 11 is a side cross-sectional view of a layer of conductive material deposited over the chalcogenide layer using conventional thin film deposition techniques;

FIG. 12 is a side cross-sectional view of the layer of chalcogenide material and the second layer of conductive material after they are etched back using conventional masking and etching techniques;

FIG. 13 is a side cross-sectional view of a second layer of insulative material that is applied using conventional thin film deposition techniques;

FIG. 14 is a side cross-sectional view of the second layer of insulating material after it is etched back;

FIG. 15 is a side cross-sectional view of the complete chalcogenide memory cell including an upper conductive grid layer;

FIG. 16 is a side cross-sectional view, which is analogous to FIG. 9, illustrating an intermediate structure after planarization of the layer of the insulative material using a conventional CMP process;

FIG. 17 is a side cross-sectional view of an etch mask formed over the insulative material layer;

FIG. 18 is a side cross-sectional view of a recess formed by etching a portion of the frustoconical shaped tip;

FIG. 19 is a side cross-sectional view of a chalcogenide material layer that is deposited using conventional thin film deposition methods;

FIG. 20 is a side cross-sectional view of a layer of conductive material deposited over the chalcogenide layer using conventional thin film deposition techniques;

FIG. 21 is a side cross-sectional view of a resulting structure after planarization of the conductive material;

FIG. 22 is an oblique cross-sectional view of a memory cell array of the present invention;

FIG. 23 is a schematic of a computer with a CPU and interacting RAM;

FIG. 24 is a side cross-sectional view of a resulting structure utilizing an optional conductive barrier layer between the conductive material and the chalcogenide material;

FIG. 25 is a side cross-sectional view of the deposition of a layer of polysilicon onto a substrate of titanium nitride in accordance with an alternate embodiment of the present invention for forming an intermediate structure;

FIG. 26 is a side cross-sectional view of the deposition of a layer of silicon oxide and a layer of resist material onto the layer of polysilicon;

FIG. 27 is a side cross-sectional view of a contact pattern that is etched in the layer of resist material and the silicon oxide layer using etching, masking, and photoresist stripping techniques;

FIG. 28 is a side cross-sectional view of the device after the resist material layer has been stripped away using strip etching techniques;

FIG. 29 is a side cross-sectional view of a portion of the layer of polysilicon material not covered by the silicon oxide layer pattern that is etched using conventional undercut isotropic etching techniques to form a sharp tip in the layer of polysilicon material;

FIG. 30 is a side cross-sectional view of the device after the contact pattern has been removed using conventional wet etch techniques;

FIG. 31 is a side cross-sectional view of the depositing of a layer of insulative material onto the layer of polysilicon material, including the tip, using conventional thin film deposition methods to isolate the layer of polysilicon material, including the tip; and

FIG. 32 is a side cross-sectional view of planarization of the layer of insulative material using a conventional chemical mechanical planarization (CMP) process.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of application Ser. No. 09/586,144 filed Jun. 2, 2000, now U.S. Pat. No. 6,294,452, issued on Sep. 25, 2001, which is a continuation of application Ser. No. 08/956,594, filed Oct. 23, 1997, now U.S. Pat. No. 6,150,253, issued Nov. 21, 2000, which is a continuation-in-part of U.S. patent application Ser. No. 08/724,816, filed Oct. 2, 1996, now U.S. Pat. No. 6,147,395, issued Nov. 14, 2000.

CLAIMS

1. A method for fabricating a memory chip, comprising: providing a substrate; forming a conductive layer over said substrate, said conductive layer formed in such a manner as to include at least one raised portion characterized by a tip having a first cross-sectional area and a base having a second cross-sectional area, said second cross-sectional area of said base being larger than said first cross-sectional area of said tip; providing an insulative material over at least a portion of said conductive layer; depositing a programmable resistive material in contact with said tip of said at least one raised portion of said conductive layer.

2. The method of claim 1, wherein depositing said programmable resistive material comprises depositing a chalcogenide material.

3. The method of claim 2, further comprising selecting said chalcogenide material from a group consisting of tellurium (Te), germanium (Ge), antimony (Sb), and combinations thereof.

4. The method of claim 3, further comprising formulating said chalcogenide material to include Te, Ge, and Sb in a ratio TeaGebSb100−(a+b), where a, b, and 100−(a+b) are in atomic percentages which total 100% of constituent elements and a≦70% and 15%≦b≦50%.

5. The method of claim 4, wherein 40%≦a≦60% and 17%≦b≦44%.

6. The method of claim 1, wherein forming said conductive layer comprises: forming a planar conductive layer over said substrate; forming an oxide layer on said planar conductive layer; patterning said oxide layer to form at least one oxide element; and etching said planar conductive layer to form said at least one raised portion characterized by said tip having said first cross-sectional area and said base having said second cross-sectional area, said second cross-sectional area of said base being larger than said first cross-sectional area of said tip.

COPYRIGHT

User acknowledges that Fairview Research and its third party providers retain all right, title and interest in and to this xml under applicable copyright laws. User acquires no ownership rights to this xml including but not limited to its format. User hereby accepts the terms and conditions of the License Agreement.