Method for increasing efficiency in a multi-processor system and multi-processor system with increased efficiency

ABSTRACT

The multi-processor system according to the present invention includes at least two processors, a system bus providing communication between the responses to commands on the system bus. One of the processors generates a snoop response to a command, associated with the same real address as the snooped command, which issued from the processor. In response to a command requesting invalidation of a cache line, a cache within the processor conditionally casts back the cache line to a transition cache in the processor. Based on the system response to the invalidation command, the transition cache either discards the cast back or converts the cast back into a command for writing the cache line in the main memory of the system. The processor also converts an exclusive read command requiring a reservation to a non-exclusive read command if that reservation has been lost prior to placing the command on the system bus. Furthermore, the transition cache in the processor may shift the memory coherency image state for a non-exclusive command, which is waiting for data to return, if a command associated with the same real address is snooped. In response to a command requesting a cache line, the cache in the processor copies that cache line to the transition cache and updates the state for the cache line. The transition cache holds the cache line until a system response is received.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

This application is a divisional of application Ser. No. 08/999,961, filed on Jan. 8, 1998 (now U.S. Pat. No. 6,260,117, issued Jul. 10, 2001), the entire contents of which are hereby incorporated by reference and which is a continuation-in-part of application Ser. No. 08/932,826 filed on Sep. 18, 1997 (now U.S. Pat. No. 6,065,098, issued Mar. 16, 2000), the entire contents of which are hereby incorporated by reference, and for which priority is claimed under 35 U.S.C. § 120.

BRIEF DESCRIPTION OF THE DRAWINGS

The present invention will become more fully understood from the detailed description given hereinbelow and the accompanying drawings which are given by way of illustration only, and thus are not limitative of the present invention, and wherein:

FIG. 1 illustrates a multi-processor system including a processor with non-inclusive caches which employs the method for obtaining multi-level cache coherency according to the present invention;

FIG. 2 illustrates the adjustments to the times at which the snoop commands are supplied to each level of cache by the processor according to the present invention;

FIG. 3 illustrates a portion of the system bus controller according to the present invention;

FIG. 4 illustrates a table showing the generation of the combined response by the priority combining logic according to the present invention;

FIG. 5 illustrates the snoop pipeline in the system bus controller according to the present invention;

FIG. 6 illustrates the timing of overlapping snooped commands;

FIG. 7 illustrates a flow chart of the method for preventing collisions between two cache queries in high level caches where one of the cache queries is the result of a snooped command;

FIG. 8 illustrates a Table which shows a higher level cache's snoop response based in part on the response from the lower level cache;

FIG. 9 illustrates a table showing the generation of a conditional retry response by the transition cache and the possible combined responses;

FIG. 10 illustrates a table showing the possible MESI state changes at the caches of a processor in response to a kill command when the MESI state for one of the caches was initially modified and the possible resulting commands output from the processor;

FIG. 11 illustrates a table showing the transition cache snoop response and possible MESI state change when a collision occurs between a first command stored at the transition cache and a later snooped second command; and

FIG. 12 illustrates a table showing the possible MESI state changes at the caches of a processor receiving a first command requesting a cache line stored therein and the resulting second command output by the processor for each possible system response to the first command.

It is respectfully suggested that FIG. 1 be printed on the face of the patent.

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 illustrates a multi-processor system including a processor with non-inclusive caches which employs the method for maintaining multi-level cache coherency and the method for increasing efficiency in a multi-processor system according to the present invention. The system includes a system bus interconnecting multiple processors and at least one processor with non-inclusive caches. The processor may include inclusive or non-inclusive caches, however, when only employing the method for increasing efficiency in a multi-processor system according to the present invention. In a preferred embodiment of this method, and for the purposes of discussion, the processor will be described with non-inclusive caches.

A main memory , one or more input/output or I/O interfaces , and a bus arbiter are also connected to the system bus . Disk drive storage devices, tape storage devices, etc. are connected to the I/O interfaces .

The multiple processors and the processor communicate over the system bus with each other, the main memory , and the I/O interfaces . The I/O interfaces control the operation of such input and output devices as disk drive storage device, tape storage devices, etc. The main memory serves as central storage for the multi-processor system, and stores, for instance, all the cache lines in the system. The bus arbiter decides which of the devices connected to the system bus drives the system bus based on any well-known protocol. Also, for each command placed on the system bus , the bus arbiter collects the snoop responses thereto, and generates as the system response the highest priority response collected.

Besides the processor , one or more of the multiple processors could also be a processor according to the present invention. As shown in FIG. 1, the processor includes a system bus controller which controls communication between the system bus and the processor . A transition cache , level one or L data cache , with controller included, and a level two or L cache controller are connected to the system bus controller . A level two or L cache , external to the processor , is connected directly to the L cache controller . The L data cache , the L cache controller and L cache are connected to the transition cache . The L data cache includes a reservation register for storing the reservation bit set by the L data cache with respect to a command, such as a store conditional, which requires a reservation to complete. As shown in FIG. 1, the system bus controller can check the status of a reservation bit stored in the reservation register . FIG. 1 further illustrates that the snoop response of the transition cache is supplied to the L data cache , and that the snoop response of the L data cache is supplied to the L cache controller .

It should be understood that the various paths illustrated in FIG. 1 have been represented in greatly simplified form for clarity. In reality, many separate data paths into and out of the various components are required. Furthermore, for the sake of clarity, many of the data and control lines have been eliminated entirely from the figures. It will also be appreciated that, for clarity, other components forming the processor , such as execution units, have been eliminated from FIG. .

The L data cache has a lower storage capacity, but faster access time, than the L cache . Also, unlike what is characteristic of conventional processors, the L cache is non-inclusive. Specifically, the L cache does not store all of the cache lines stored in the L data cache . Consequently, the response to a snooped command provided by the L cache controller does not represent the response to the same snooped command which could be issued by the L data cache .

As implied above, the L cache controller controls the communication of data and commands to the L cache . As illustrated in FIG. 1, the transition cache handles the communication of commands and data between the system bus controller , the L data cache and, via the L cache controller , the L cache . As mentioned above, for the purpose of clarity, the connections to effect such communication between the transition cache and the other components of the processor have not been illustrated in detail. Also, any direct connections between the L data cache and the L cache have also been eliminated for clarity.

The transition cache is a transition cache such as disclosed in application Ser. Nos. 08/761,378; 08/761,379; and 08/761,380, all filed Dec. 9, 1996; the entire contents of all are hereby incorporated by reference. Alternatively, however, the transition cache could be replaced by cache line buffers which maintain the memory coherency image state of each cache line stored therein.

For purposes of discussion, the present invention will be discussed using the well-known MESI state protocol as the memory coherency image state protocol employed by the multi-processor system. It should be understood, however, that any memory coherency image protocol could be used with the present invention.

Generating a Combined Response at Processor

Next, the operation of the processor with respect to generating a single combined response to a snooped command will be discussed. As described in detail below, the processor with non-inclusive caches according to the present invention includes a system bus controller which snoops commands on a system bus , and delays supplying those snooped commands to lower levels of cache. The delay times are set such that each lower level cache will output a snoop response at a known point in time. Based on the snoop response from each level of cache, the system bus controller generates a single combined response, and outputs the combined response on the system bus . Besides generating snoop responses based on the snooped commands, higher level caches also generate their snoop responses based on the snoop responses of lower level caches. In this manner, the memory coherency image states in the higher level caches are efficiently updated.

During operation, the system bus controller snoops commands on the system bus . The system bus controller then supplies the snooped command to the transition cache , the L data cache and the L cache controller . The system bus controller , however, does not simultaneously supply the snooped command to the transition cache , the L data cache , and the L cache controller .

As discussed above, the L data cache has a faster access time then the L cache . Similarly, the transition cache , which has a smaller storage capacity than even the L data cache , has a faster access time than the L data cache . As shown in FIG. 2, the system bus controller adjusts the time at which the snooped command is supplied to the transition cache , the L cache and the L cache controller such that the responses to the snooped command generated by the transition cache , the L data cache and the L cache controller are output at a known or a fixed time. More specifically, as shown in FIG. 2, the snooped command is supplied to the L cache controller first, then after a predetermined period of time, the snooped command is supplied to the L data cache . After a further predetermined period of time, the snooped command is supplied to the transition cache .

Even in view of the delay, the transition cache will generate its response prior to the L data cache and the L cache controller generating responses. Similarly, the L data cache will generate a response to the snooped command prior to the L cache controller generating a response. As stated above, the delays in supplying the snooped command to the transition cache and the L data cache are set such that the transition cache and the L data cache output their respective responses at known or fixed points in time.

When a cache such as the transition cache , the L data cache , and the L cache controller receive a snooped command, the cache determines whether or not the real address associated with the snooped command matches the real address of any cache lines stored therein. If a match is found, the MESI state for that cache line is modified in a well-known manner based on the snooped command, and regardless of whether a match is found, a snoop response is generated. In the L data cache , the MESI state and snoop response are further modified based on the snoop response of the transition cache . Similarly, the MESI state and snoop response of the L cache controller are further modified based on the snoop response of the L data cache .

FIG. 8 illustrates the snoop responses generated by a higher level L(n+1) cache given the MESI state of the higher level L(n+1) cache and the snoop response from the lower level L(n) cache. In the figures, “M” stands for Modified, “E” stands for Exclusive, “S” stands for shared, “O” stands for shared owner and “I” stands for invalid. Also, “→” indicates a change in the MESI state based on the snooped command.

The system bus controller receives the snoop responses from the transition cache , the L data cache , and the L cache controller . The portion of the system bus controller handling the snoop responses from the transition cache , the L data cache , and the L cache is illustrated in greater detail in FIG. . As shown in FIG. 3, the snoop responses from the transition cache , the L data cache and the L cache controller are received by priority response combining logic . The response from the transition cache , however, is delayed by a first delay and a second delay prior to receipt by the priority response combining logic . Also, the snoop response from the L data cache is delayed by a third delay prior to receipt by the priority response combining logic . The first, second and third delays , and delay a signal by the same period of time in a preferred embodiment of the present invention. Also, the delay time of the first, second and third delays , and is set such that the priority response combining logic receives the response from the transition cache , the L data cache and the L cache controller substantially at the same time. While not forming a part of this method, as described in detail below, the priority response combining logic also selectively receives the system response for a snooped command. The priority response combining logic then generates a single combined response based on the responses from the transition cache , the L data cache and the L cache controller in accordance with the Table shown in FIG. .

As shown in FIG. 3, the priority response combining logic outputs the combined response to a snoop pipeline . The snoop pipeline is illustrated in FIG. . As shown in FIG. 5, when the system bus controller snoops a command, the command is stored in the snoop pipeline , i.e., memory in the system bus controller . As time goes on, the snooped command flows through the snoop pipeline . The operations taking place with respect to the snooped command are illustrated to the right of the snoop pipeline in chronological order. As shown, the snooped command is sent to the L cache controller , then sent to the L data cache , and finally, sent to the transition cache . At some point in time prior to the receipt of the combined response from the priority response combining logic , portions of the snooped command are no longer needed, and thus, as shown in FIG. 5, the amount of information stored with respect to a snooped command decreases. Soon afterwards, the combined response output by the priority response combining logic is stored with the snooped command. If a system response to the snooped command is not required to generate a combined response, the combined response to the snooped command is then output on the system bus by the system bus controller , and later a system response is received and associated with the snooped command. Otherwise, generation of a combined response is delayed until the system response is received. Eventually, because the snoop pipeline has a finite length, the snooped command is removed therefrom. As shown in FIG. 6, pipelining of snooped commands allows overlap thereof.

Preventing Collision between L Cache Queries

Because of the longer access time of the L cache , the possibility of a collision between two L queries, the second of which is the result of a snooped command, exists.

A collision occurs when the two L queries map to the same cache address, i.e., have the same congruence class. Because of this collision, an improper response to the snooped command can be generated. For instance, suppose that the L cache controller receives a fill request indicating a miss in the L data cache , and in response the L cache performs an aging castback, discussed below.

Because caches have limited storage space, more than one real address can map to the same cache address. When this occurs between a cache line currently stored and a cache line to be received, the currently stored cache line is sent to, for instance, the main memory . Treating the currently stored cache line in this manner is called an aging castback.

When the L cache controller performs an aging castback with respect to a cache line stored in the L cache , the cache line being castback is first transferred to the transition cache . The transition cache then transfers the cache line to the main memory via the system bus controller and the system bus .

Next, suppose that the L cache controller snoops a command having a real address which maps to the same cache address as the cache line which was the subject of the aging castback. If this collision were not prevented, the L cache controller would generate a null response because the cache line was castback. If, however, the cache line had not been completely transferred to the transition cache yet, then the transition cache would also output a null response. Absent the collision, the L cache controller , or perhaps the transition cache , would have generated a non-null response. Therefore, the combined response issued by the system bus controller may be improper.

The present invention avoids this problem by preventing such collisions. Namely, when the real address for a snooped command maps to the same cache address as another L query, the snooped command is not processed. Instead, the L cache controller generates a retry response with respect to the snooped command, which instructs the system to retry issuing this command at a later point in time.

The method for preventing collisions between a snooped command and another command will be described referring to the flow chart illustrated in FIG. . In step S, the L cache controller receives a snooped command. Then, in step S, the L cache controller accesses the tag array or directory for the L cache , and stores the snooped command. In response to the tag array access, the L cache controller will determine if the real address of a cache line stored in L cache matches the real address associated with the snooped command. If a match exists, the L cache controller accesses, from the L cache , the MESI state associated with the cache line, and, in step S discussed below, generates a snoop response based on the MESI state. If no match exists, the null snoop response will be generated in step S.

In step S, the L cache controller compares the cache address, to which the real address of the snooped command maps, to the cache addresses associated with the L queries made one cycle ago and two cycles ago. Then in step S, the L cache controller determines whether a cache address match exists. If a match is found, the L cache controller will output a retry response with respect to the snooped command in step S. As shown in FIG. 4, because the L cache controller outputs a retry response, the system bus controller outputs a retry response as the combined response. As mentioned above, the retry response instructs the system to retry issuing the command at a later point in time. If no match is found, the L cache controller waits for, in step S, the response to the tag array access made in step S, and once that response is received, the L cache controller outputs a snoop response to the snooped command. In this manner, collisions between a snooped command and other commands can be detected and prevented.

Conditional Retry

Besides the responses discussed above with respect to FIG. 4, the transition cache also may generate a conditional retry snoop response. When the transition cache snoops a command from another processor that is associated with the same real address, i.e., cache line, as a command output by the processor , the transition cache may output a conditional retry snoop response. Depending on the system response to the command output by the processor , the system bus controller treats the conditional retry snoop response as a retry snoop response or a not retry snoop response, i.e., a response other than a retry snoop response. In this manner, depending on the system response to the command output by the processor , the system bus controller may not output a retry response as the combined response even though a collision between commands has occurred.

FIG. 9 illustrates a table, to be appended to the table of FIG. 4, that shows when a conditional retry snoop response is generated by the transition cache and the possible combined responses output from the system bus controller . When the processor puts a first command on the system bus , the status and a copy of the first command is maintained by the transition cache . The transition cache snoops the first command on the system bus , and updates the MESI state for the first command. Namely, the transition cache sets the MESI state for the first command to fill Pending.

Also, the MESI state of the cache line associated with the first command in the L data cache and the L cache will be known or unknown based on the type of the first command. For instance, if the first command is a cache line read, then the MESI state in the L data cache and/or the L cache is invalid. However, if the first command is a request for ownership of a cache line, the MESI state in the L cache and/or L cache is unknown.

If, while in the fill Pending state, the transition cache snoops a second command associated with the same real address as the first command, then the transition cache generates either a retry or conditional retry snoop response. As shown in FIG. 9, the transition cache generates a retry snoop response if the second command is an exclusive command or if the L data cache and/or L cache MESI states for the cache line associated with the real address are unknown. The transition cache generates a conditional retry snoop response if the second command is a non-exclusive command and the MESI states in the L data cache and/or the L cache for the cache line associated with the real address are known to be invalid.

Assuming that the transition cache generates a conditional retry snoop response, the system bus controller delays generating a combined response until a system response is received for the first command. If the system response to the first command is retry, then as shown in FIG. 9, the system bus controller does not generate a combined response of retry. If, however, the system response to the first command is not retry, then the system bus controller generates retry as the combined response.

As discussed above, conventionally the second command causing a collision always received a retry response regardless of the system response to the first command involved in the collision. The present invention, however, provides for instances where a retry response is not generated even in the event of a collision; thus, reducing the number of retries placed on the system bus and increasing efficiency of the multi-processor system.

Conditional Castback

Besides an aging castback, the L data cache and L cache controller according to the present invention perform conditional castbacks. A conditional castback allows the transition cache to optionally perform a write to main memory based on the system response to the command causing the generation of the conditional castback. In this manner, the number of writes to main memory is reduced.

When snooping a kill command which requests that an identified cache line be invalidated without regard to the current MESI state, the L data cache and L cache controller generate a conditional castback command if the current MESI state is Modified. Namely, the modified data is copied to the transition cache and marked as a conditional castback. The L data cache and/or L cache controller then set the MESI state for the cache line to invalid.

The transition cache holds the modified data until a system response to the kill command is received. The transition cache then processes the conditional castback command based on the system response to the kill command as shown by the table in FIG. . FIG. 10 also illustrates the MESI state change taking place at the L data cache and the L cache .

As shown in FIG. 10, if the system response to the kill command is not retry, then the transition cache discards the conditional castback command because the kill command has completed normally. If, however, the system response to the kill command is retry, the transition cache converts the conditional castback to a memory write command for writing the modified data in the main memory .

Because the conditional castback is discarded in the event the kill command completes normally, the number of writes to main memory is reduced as well as the number of retries on the system bus . Accordingly, system resources are not tied up.

Converting Exclusive Atomic Reads to Non-Exclusive, Non-Atomic Reads

As is well known, the load and reserve instruction and the store conditional instruction, together, permit atomic update, i.e., performed in its entirety with no visible fragmentation, of a storage location. The load and reserve instruction, when completed, obtains a reservation for a memory location, and causes the L data cache to store a bit indicating the obtained reservation in the reservation register . The store conditional instruction can only complete if the reservation is valid when data returns to the L data cache .

Conventionally, in response to a store conditional instruction from the processor, the system bus controller therefor outputs an exclusive read regardless of whether the reservation is still valid. This causes any cache storing the cache line associated with the exclusive read to invalidate that cache line, i.e., MESI state set to Invalid. By contrast, prior to outputting an exclusive read, the system bus controller of the processor according to the present invention checks the validity of the reservation for this command. If the reservation has been lost, then the system bus controller converts the exclusive read command to a non-exclusive read command.

Because the exclusive read issued from the L data cache , a copy thereof is stored in the transition cache , which tracks the progress of the command. Namely, the transition cache snoops the non-exclusive read on the system bus , recognizes the non-exclusive read as being converted from the exclusive read command stored therein, and converts the exclusive read stored therein to a non-exclusive read.

When data returns in response to the non-exclusive read, the data is transferred to the L data cache via the transition cache , and the store conditional completes but the MESI state therefor is not updated because the reservation was lost.

Because the exclusive read is converted to a non-exclusive read, the present invention prevents the cache line associated with the non-exclusive read from being unnecessarily and undesirably invalidated in the caches of the other processors . Accordingly, efficiency is increased by eliminating the need for those other processors to re-validate the cache line.

Shifting Transition Cache State

With the transition cache implementation of present invention, a collision where another processor wants a copy of the cache line that is being filled on this processor can be detected. Most designs allow one processor to get the cache line when in transition MESI states. These designs retry all other processor accesses during this transitional period of time. The present invention allows for shifting the MESI state of the filling line at the transition cache , i.e., without interacting with the L data cache and L cache controller . As a result, the present invention allows sharing with no performance impact during the time the transition cache handles the cache line fill, and reduces the number of retries on the system bus .

As discussed previously, when a first command such as a non-exclusive read command is output by the system bus controller , the transition cache snoops the non-exclusive read command on the system bus and changes the MESI state for the non-exclusive read command to pending. Once a system response is received, the transition cache updates the MESI state to one of Exclusive, Shared or shared Owner. The transition cache then waits for the data associated with the non-exclusive read command to arrive.

If the transition cache snoops a second command associated with the same real address as the non-exclusive read command, the transition cache checks the status of the non-exclusive read command to determine if data has arrived at the transition cache in response to the non-exclusive read command. As shown in FIG. 11, based on the determination of whether data has begun to arrive and whether the snooped second command is exclusive or non-exclusive, the transition cache changes the MESI state for the first command and generates a snoop response to the second command.

Namely, if data has started to arrive, the transition cache generates a retry snoop response and does not change the MESI state of the first command. If data has not started to arrive and the second command is an exclusive command, the transition cache generates a null snoop response and changes the MESI state for the first command to Invalid. If the data has not started to arrive and the second command is a non-exclusive command, the transition cache generates a shared snoop response and changes the MESI state for the first command to Shared.

As further shown in FIG. 11, if the first command is an exclusive command, then the transition cache outputs a retry snoop response and the MESI state for the first command remains unchanged.

Accordingly, the present invention allows for shifting the MESI state of a non-exclusive command at the transition cache such that sharing with no performance impact is allowed and the number of retries on the system bus is reduced.

Converting Cache-to-Cache Transfer to a Memory Write

This technique of the present invention allows the L data cache and L cache controller to immediately update the MESI state of a requested cache line even if the read command requesting that cache line receives a retry system response. Also, the response to the read command is converted into a write command if the system response to that read command is a retry and the response includes modified data.

When the processor receives a read command requesting a cache line and the cache line is stored in the L data cache and/or the L cache , the one of the L data cache and the L cache having the highest MESI state, in the order of Modified, Exclusive shared Owner and Shared, copies the cache line to the transition cache . The L data cache and/or the L cache which store the cache line then update the MESI state therefor as shown in the table of FIG. .

The system bus controller receives the cache line and holds the cache line until the system response to the read command is received. FIG. 12 illustrates a table showing how the system bus controller processes the cache line based on the system response. As shown in FIG. 12, if the system response to the read command is not retry, the system bus controller sources the cache line to the system bus . If, however, the system response is retry and the MESI state for the cache line in one of the L data cache and the L cache , prior to being updated, was modified, then the system bus controller converts the response to the read command to a memory write for writing the cache line in the main memory . It should be noted that because the system bus receives the snoop response of the L data cache and the L cache to the read command, the system bus controller is notified if the cache line includes modified data.

If the cache line does not include modified data and the system response to the read command is retry, then the system bus controller discards the cache line.

By transferring the cache line to the transition cache , the MESI state of the cache line in the L data cache and/or the L cache can be immediately updated. Also, by waiting for the system response to the read command, the cache line may be written to the main memory to improve the efficiency with which the main memory is updated with modified data.

It should be understood that the present invention is not limited to a processor with only two levels of cache. Instead, additional levels of non-inclusive cache could be included, with the method for preventing collisions according to the present invention being applied to the second and higher levels of cache.

While the invention has been described with what is presently considered the most practical and preferred embodiments, it is to be understood that the invention is not limited to the disclosed embodiments, but on the contrary, is intended to cover various modifications and equivalent arrangements included within the spirit and scope of the appended claims.

CLAIMS

1. A multi-processor system, comprising: at least first and second processors; a system bus providing communication between said first and second processors; a bus arbiter generating system responses to commands on said system bus; and wherein said first processor includes at least a level one cache, a system bus controller controlling communication between said first processor and said system bus, and a transition cache controlling and tracking communication between each level of cache and said system bus controller; and said system bus controller checks a reservation of a first command, said first command being a system bus command for transferring data on said system bus which requires a reservation, generated by said level one cache prior to placing said first command on said system bus, and converts said first command into a second command, said second command being a system bus command for transferring data on said system bus which does not require a reservation, when said reservation for said first command has been lost; and said transition cache receives said first command from said level one cache and communicates said first command to said system bus controller, snoops said second command on said system bus, and converts said first command stored therein into said second command based on said snooping of said second command.

2. The system of claim 1, wherein said first command is an exclusive command and said second command is a non-exclusive command.

3. The system of claim 1, wherein said first command is a store conditional.

4. A method for increasing communication efficiency in a multi-processor system, comprising: generating, at a level one cache in a processor, a first command requiring a reservation, said first command being a system bus command for transferring data on a system bus of said multi-processor system, said system bus providing communication between processors in said multi-processor system; checking said reservation prior to placing said first command on said system bus; converting said first command into a second command, which does not require a reservation, said second command being a system bus command for transferring data on said system bus, when said checking step indicates that said reservation for said first command has been lost; transferring said first command from said level one cache to a transition cache in said processor after said generating step; copying said first command from said transition cache to a system bus controller in said processor; wherein said checking and converting steps are performed by said system bus controller; and further comprising, snooping, by said transition cache, said second command on said system bus; and converting said first command stored in said transition cache into said second command based on said snooping of said second command.

5. The method of claim 4, wherein said first command is an exclusive command and said second command is a non-exclusive command.

6. The method of claim 4, wherein said first command is a store conditional.

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