Virtual PCI device apparatus and method

ABSTRACT

Virtual PCI bus appears from the perspective of a computer program to be a part of a physical hierarchical PCI bus structure residing behind a host-to-PCI bridge. Devices that are physically located on the host bus side of the host-to-PCI bridge may appear as virtual devices residing on the virtual PCI bus allowing the physical devices to participate in device independent initialization and system resource allocation generally available only to PCI compliant devices. Processor initiated host bus cycles targeted to the virtual PCI device may be intercepted and redirected to the physical device.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION

Various embodiments of the provide for the integration of devices, such as network controllers, mass storage controllers, display controllers, multimedia devices, communication devices, and other devices, into a host bus processor as well as the efficient coupling of a device to a processor host bus. Select aspects of PCI protocol may be adhered to, enabling software support for these devices that is generally available only to PCI compliant devices. The present invention may provide, in some systems, at least one of a number of advantages over methods of prior art including: increased system performance, increased device performance, simpler initialization and configuration of all devices in a system, increased robustness in the system resource allocation process, lower overall cost and decreased physical board/chip space as well as enabling the allocation of a subset of the address space assigned to a physical PCI bus to a device residing on a host bus. Additionally, the present invention may enable integration of devices, which appear to computer programs as having many of the characteristics of a PCI compliant device, into a host processor, resulting in a number of advantages such as lower overall system cost, less space, reduction in processor-chip pin-count and increased bandwidth on PCI busses, increased system performance or increased device performance.

FIGS. 1A, B, , and show block diagrams of systems , , and for explaining various embodiments of the present invention. Processor may represent any one processor coupled to host bus . Alternatively processor may represent two or more processors coupled to host bus .

Systems , , , may include a host bus device , , such as a network controller, mass storage controller, display controller, multimedia device, communication device, or other device. Host bus device , , may be coupled to host bus through an interface in a manner that allows host bus to be monitored and allows processor initiated host bus cycles, which are targeted to non-existent virtual PCI device , to be intercepted by host bus device .

Host bus device , , may include a monitor circuit that is coupled to host bus for tracking host bus cycles. Monitor circuit may capture select information during each host bus cycle and identifies select host bus cycles that are to be snooped or intercepted. Read cycles may be intercepted by driving select host bus data signals to transfer data to host bus and then completing the cycle. A cycle, initiated by processor , is completed by informing the active processor when to terminate the cycle pursuant to the particular protocol employed by the host bus . Write cycles may be intercepted by latching the value of select host bus data signals on host bus write cycles and then completing the cycle. Host bus cycles may be snooped by reading and storing select host bus cycle information in a storage while the cycle is typically completed by another device coupled to the host bus .

Host bus device , , may include storage that is coupled to host bus to allow the contents of storage to be accessed through the host bus . Various specific embodiments of storage may include registers , , that reside in system configuration space or random access memory (RAM), registers, or data ports that reside in system I/O or memory address space.

PCI protocol provides for a certain number of addressable slots on each PCI bus in which a PCI device may reside. A PCI-to-PCI bridge is a PCI device that provides a transfer path between two PCI busses. A computer program typically assigns each PCI bus directly behind a detected PCI-to-PCI bridge a unique bus number. The PCI bus number and slot number combination provide a unique identifier that may be used by computer programs to select any particular PCI device installed in a system through configuration space. PCI addressing and routing protocol generally anticipates a physical hierarchal bus structure in which host bus cycles, targeted to a particular PCI device are physically routed through a host-to-PCI bridge and possibly through one or more PCI-to-PCI bridges to generate a cycle on the particular PCI bus in which the targeted PCI device resides. Each PCI bus is defined to be behind any PCI bus in the physical/virtual data transfer path between that PCI bus and host bus.

For purposes of this specification a primary PCI bus may be bus number and be the bus directly behind the host-to-PCI bridge, but it may also be any PCI bus that is behind bus number in which virtual PCI device appears to be behind and it is consistent with the methods of the present inventions for there to be more then one primary PCI bus in a particular system. Additionally the primary PCI bus may be an actual PCI bus or it may be virtual. The terms virtual and logical, for purposes of this specification, refer to the perspective of a computer program running on any one or more processor where the program has an impression of a physical device or structure that may not be reflective of an actual physical device or structure. Virtual PCI device logically resides on a PCI bus , which is either an extension of primary PCI bus or one of its subordinates (i.e. busses that reside behind primary PCI bus ).

A host-to-PCI bridge , , may facilitate the translation and routing of a select host bus cycles to a primary PCI bus and its subordinate busses. Host-to-PCI bridge , , may include, a host bus interface , a PCI bus interface , storage , storage and control circuit to track host bus cycles to determine, for each host bus cycle, whether to route the host bus cycle to an actual primary PCI bus . To make this determination, control circuit consults storage , which identifies address space allocated to primary PCI bus and its subordinates, and storage , which identifies address space allocated to virtual PCI device or possibly other virtual devices. Storage and may hold information in the form of bus numbers, memory address ranges, I/O address ranges or other similar information. The information in storage , that indicates the address ranges allocated to virtual PCI device (or in more complex configurations to all or a group of virtual devices or busses), may generally be a subset of the address space in storage , which is allocated to primary PCI bus and its subordinates. Host bus cycles which are targeted to virtual PCI device are allowed to be intercepted by host bus device , , .

In a system where host bus utilizes the protocol of a Pentium™ 3 or 4 processor, host-to-PCI bridge , , may be the responder for all host bus cycles insuring that all host bus cycles are completed according to host bus protocol, and host bus device may claim select host bus cycles which it intercepts.

The information required to identify host bus cycles targeted to virtual PCI device and the manner in which this information is obtained, may depend on the bus structure of the particular system. The unique bus-device number combination of virtual PCI device may be hardwired or preprogrammed into both the host bus device and host-to-PCI bridge in a system in which virtual PCI device resides logically on primary PCI bus .

It is consistent with the methods of the present invention for a system , , , to have two, three or more host bus devices , , or to have two, three or more processors with each having one or more host bus devices , , integrated into it. The methods of the present invention may be applied to a system comprised of a plurality of distinct host bus devices , which are each to be associated with one of a plurality of distinct virtual PCI devices . Host bus cycles targeted to any one of the plurality of virtual PCI devices are not forwarded to primary PCI bus by host-to-PCI bridge ; rather, one of the host bus devices is allowed to intercept the cycle. More than one host bus device may be associated with a particular virtual PCI device , such that the two or more host bus devices utilize the system resources allocated to the particular virtual PCI device. Conversely, a single host bus device may be associated with more than one virtual PCI device . In addition, a host bus device may support multiple functions in accordance with PCI protocol. A scheme for preventing multiple host bus devices from intercepting cycles to the same virtual PCI device , may be accomplished by hardwiring or preprogramming each host bus device with a unique bus number-device number combination for identifying its associated virtual PCI device .

FIG. 1A shows host bus device coupled to host bus through interface , which is distinct from the host bus interface to processor . FIG. 1B shows an alternate configuration consistent with the methods of the present invention, where processor and host bus device are coupled to host bus through an internal bus and a shared host bus interface . The system of FIG. 1B can result from integrating host bus device and processor into a single circuit package.

FIG. 2 shows a system for explaining an embodiment of the present invention pursuant to the teachings for system shown in FIG. . System includes a virtual PCI device , which appears from the perspective of a computer program running on one or more processors , to include 256 8-bit configuration registers that are accessible through configuration space. Only the necessary and relevant configuration registers appear to be implemented. In accordance with PCI protocol, a computer program may initiate accesses to virtual configuration registers to accomplish one or more functions that include detecting the presence of virtual PCI device , identifying the vendor and device type determining virtual device's system resource requirements, providing for full device relocation, interrupt binding, installation, configuration, booting without user intervention, and including virtual PCI device in the system map construction.

Host bus device may include host bus storage , which in this embodiment, is comprised of PCI compliant configuration registers . Only the necessary and relevant registers are implemented. Monitor circuit tracks host bus cycles and identifies host bus cycles targeted to virtual configuration registers , which are intercepted and redirected to access the host bus device configuration registers . As a result, a computer program executing on processor can access host bus device configuration registers by initiating a host bus cycle targeted for the configuration registers of virtual PCI device . In this manner, host bus device participates in an initialization and configuration procedure for assigning system resources that is generally available only to PCI devices.

Configuration cycles are generated in system through either one of two mapping mechanisms provided by PCI protocol. Mechanism one is an indexing scheme in which two fixed locations in processor I/O space are reserved for a configuration-address register and a configuration-data register , which are typically incorporated into a host-to-PCI bridge . Configuration-address register enables or disables configuration space and is written by a computer program to identify a particular PCI device and specific configuration register by specifying the bus number, device number, function number, and register number for which a subsequent configuration cycle is intended. Subsequent DWORD read and write host bus cycles targeted to configuration-data register are translated and routed, typically by host-to-PCI bridge , into PCI compliant configuration cycles; however, host bus cycles targeted to the configuration registers of virtual PCI device are intercepted by host bus device rather then be routed by host-to-PCI bridge as anticipated by PCI protocol.

A system that supports mechanism one, may provide a mirror register that is included in storage , which holds select information obtained through snooping. Host bus write cycles targeted to configuration-address register may be snooped by host bus device and the data transferred in the snooped cycle may be stored in mirror register which then reflects the contents of configuration-address register . Monitor circuit may consult mirror register to identify subsequent DWORD host bus cycles targeted to configuration-data register that are intended to access virtual configuration registers . These identified cycles may be intercepted by host bus device and redirected to access corresponding configuration registers in host bus device .

Alternately, system may support mechanism two, where a configuration-space-enable register (not shown) and a forward register (not shown), which typically reside in host-to-PCI bridge , are written to by a computer program to specify 4k byte of configuration space to be mapped into a fixed location in processor I/O address space. A system , designed to supports mechanism two may provide a mirror register to store snooped host bus write cycles targeted to configuration-space-enable register (not shown) and forward register (not shown). Mirror register may be consulted by monitor circuit to identify host bus cycles that are targeted to virtual device's configuration registers . Identified cycles may be intercepted by host bus device and redirected to access corresponding configuration registers in host bus device .

Pursuant to PCI protocol, configuration registers may be utilized by a computer program to allocate system resources that include interrupts, processor memory address space, processor I/O address space, and ROM (read only memory) address space which is a range of processor memory address space reserved for ROMs. A computer program may initiate accesses to non-existent virtual configuration registers to determine virtual PCI device's system requirements and allocate resources to virtual PCI device by writing to select configuration registers . A computer program may also access virtual device's configuration registers for handling catastrophic errors as well as executing and obtaining status of a built in self-test (BIST).

Optionally, host bus device configuration registers may be implemented to indicate a request for specific system resources such as one or more ranges of memory space or I/O space to be assigned to virtual PCI device . A portion of internal storage may be mapped by a computer program into this address space for access through the host bus . After a computer program assigns address space to virtual PCI device , monitor circuit , in this optional embodiment, may consult the appropriate configuration registers to identify whether a host bus cycle is targeted to memory or I/O space allocated to virtual PCI device . These identified cycles may be intercepted by host bus device and redirected to access host bus storage .

Both the host bus device and host-to-PCI bridge may be aware of the bus number and device number of virtual PCI device . This information may be hardwired, preprogrammed, or provided by a program during system initialization and is used to identify host bus cycles targeted to virtual PCI device configuration space. Host-to-PCI bridge may learn the address space allocated to virtual PCI device by snooping select host bus write cycles targeted to the particular virtual configuration registers which specify the address space allocated to virtual PCI device .

FIG. 3 shows a system , for explaining an embodiment of the present invention, pursuant to the teachings for system and system . System implements mechanism one for accessing configuration space. System may be comprised of a primary virtual PCI-to-PCI (P—P) bridge that may appear, to a computer program running on a processor , as residing on primary PCI bus and may appear as a bridge to primary virtual PCI bus . Virtual PCI device may appear, to a computer program running on processor as residing on primary virtual bus .

Both the host bus device and host-to-PCI bridge , in this embodiment, are aware of the bus number and device number in which primary virtual P—P bridge resides and host bus device is aware of the device number of virtual PCI device . This information may be provided by an initialization program or be hardwired or preprogrammed.

Host-to-PCI bridge may include storage , which in this embodiment is written by a computer program, such as a Plug-and-Play™ resource allocation program, to assign address space to primary PCI bus , which encompasses all address space assigned to virtual device . Information stored in storage may include the bus numbers of virtual busses (not shown) that may reside behind primary PCI bus : bus numbers are commonly sufficient information to determine the configuration space allocated to primary PCI bus and its subordinates. Optionally, storage may include the memory space or I/O space allocated to primary PCI bus and any subordinates. In this embodiment, pursuant to Plug-and-Play™ protocol, the address space allocated to primary PCI bus typically encompasses the address space allocated to any optional subordinate busses (not shown) and virtual PCI device resulting in easy and efficient decode by host-to-PCI bridge for identifying host bus cycles targeted to virtual PCI bus and any optional subordinate virtual busses.

Host-to-PCI bridge may include bridge configuration registers that are consulted by control circuit to identify host bus cycles targeted to the virtual configuration registers of primary virtual P—P bridge and to route these identified cycles to the Host-to-PCI bridge configuration registers . Control circuit , in this embodiment, may consult both the bridge configuration registers and storage and storage to determine whether to route host bus cycles to primary PCI bus .

Host bus device may snoop host bus cycles targeted to the configuration registers of primary virtual P—P bridge , to learn the bus number assigned by a computer program to primary virtual PCI bus and store this information in storage , which holds select information obtained through snooping. Systems having only one host bus device may arbitrarily assign a device number to virtual PCI device . Systems with multiple host bus devices may require a mechanism for associating each host bus device with a distinct virtual PCI device , such as providing each with a unique device number (i.e. slot number), which may be hardwired, preprogrammed, or stored by an initialization program.

FIG. 4 shows a system for explaining an embodiment of the present invention, pursuant to the teachings for system shown in FIG. . Host bus device may conform to the description given for host bus device and . System implements mechanism one for accessing configuration space. System is further comprised of a secondary virtual P—P bridge , which directly interfaces a secondary virtual PCI bus . Secondary virtual P—P bridge , may appear from the perspective of a computer program running on a processor , as residing on primary virtual PCI bus and virtual PCI device may reside logically on secondary virtual PCI bus .

The secondary virtual bus is subordinate to primary virtual PCI bus , and, in this embodiment, the address space allocated to secondary virtual bus and virtual PCI device are within the address space allocated to the primary virtual PCI bus . Host-to-PCI bridge may consult storage to identify and route host bus cycles targeted for primary PCI bus and its subordinates, and consult storage to identify host bus cycles that are targeted to primary virtual bus and its subordinates. Host bus cycles targeted to primary virtual bus and its subordinates are not forwarded to primary PCI bus but are allowed to be intercepted by a host bus device . Host-to-PCI bridge may complete (i.e. terminate) intercepted host bus cycles according to host bus protocol.

Host bus device may include storage , which is coupled to the host bus and accessible by processor . Storage may be comprised of device configuration registers , which are accessed by host bus cycles targeted to the configuration registers of virtual PCI device . In addition, storage may be further comprised of bridge configuration registers which are accesses by a host bus cycles targeted to the virtual configuration registers of virtual secondary P—P bridge .

Similar to system , both the host bus device and host-to-PCI bridge , in this embodiment, are aware of the bus number and device number in which primary virtual P—P bridge resides. This information may be provided by an initialization program, hardwired or preprogrammed. Additionally, host bus device includes monitor circuit , which, in this embodiment, may learn the bus numbers assigned to primary virtual PCI bus and its subordinates by snooping host bus cycles targeted to the configuration registers of primary virtual P—P bridge . This information acquired through snooping may be stored in storage . In a system that consist of a single host bus device , the device number of the secondary virtual P—P bridge may be assigned arbitrarily.

In a system with a multiple host bus devices , a mechanism is required to associate each host bus device with a distinct secondary virtual P—P bridge such as assigning a unique device number for the associated secondary virtual P—P bridge to each host bus device , which may be hardwired, preprogrammed, or assigned by an initialization program. Each host bus device may consult its internal configuration registers , after it is written by a computer program, to determine the bus number assigned to the secondary virtual bus that directly behinds its associated secondary virtual P—P bridge and then arbitrarily assign a device number to each one or more virtual PCI devices . This information may be consulted by monitor circuit to identify of host bus cycles targeted to the virtual PCI device in a similar manner as described for system . Each host bus device may include multiple physical devices which are each associated with a distinct virtual device logically residing on its associated secondary virtual PCI bus . Plug and Play™ programs typically group resources assigned to all virtual devices residing behind each secondary virtual P—P bridge resulting in easy decode of host bus cycles by each host bus device for identifying cycles to be intercepted. For example, a single memory address range may be allocated to the secondary virtual P—P bridge that encompasses the multiple ranges allocated to each device.

FIG. 5 shows a flow diagram for explaining a method of the present invention that may be utilized by systems , , , and executed by monitor circuit . Start may be a host bus reset, which will result in storage and registers being set to default values. The following steps may be executed for each host bus cycle. The step of capturing involves waiting for a host bus cycle, then receiving and latching select host bus address and control signals that indicate the target for the current host bus cycle. The next step of assessing (step ) includes evaluating each captured cycle to determine whether to enter intercept step or to enter snooping step (step ). Snooping (step ) involves receiving and storing in storage select host bus data signals . The step of assessing (step ) includes evaluating each captured cycle to determine whether to do nothing for the current cycle and enter step to capture the next host bus cycle or to enter intercept the cycle (step ), which causes the current host bus cycle to be routed to access (i.e. read or write) the appropriate locations within host bus storage . Step and may be executed in parallel or either step , may precede the other.

FIGS. 6A and 6B show flow diagrams for explaining a method executed by monitor circuit of system , which is shown in FIG. . Start (step ) and capturing (step ) may be the same as described for steps and , respectively. Assessing (step ) and snooping (step ) are accomplished with steps , , and . Likewise assessing step and intercepting step are accomplished with steps , , , , , and . Assessing steps - may take place substantially in parallel during the address phase of a host bus cycle, and if snooping step , or intercepting step , , is executed, then the snooping or intercepting step may take place during the data phase of a host bus cycle. Snooped cycles may be completed (e.g. terminated) by a device other than host bus device and intercepted cycles may be completed by the host bus device .

Assessing step includes an evaluation of whether the current captured host bus cycle is targeted to configuration-address register . A positive evaluation results in step being entered and the data transferred by the current captured cycle is snooped and some or all of this data is stored in mirror register . A negative evaluation results in step being entered.

Assessing step includes an evaluation of whether the captured host bus cycle is targeted to the specific virtual configuration registers for assigning a bus number to primary virtual P—P bridge . A positive evaluation requires configuration-address register (as reflected by contents of mirror register ) to have a value indicating that configuration space is enabled and a value that is currently pointing to the specific configuration register of primary virtual P—P bridge that specifies the bus number assigned to primary virtual bus . A positive evaluation also requires the captured read or write host bus cycle to be targeted to configuration-data register . A positive evaluation in step results in snooping step being entered where some or all host bus data transferred in the current cycle being latched and stored in storage .

Assessing step includes an evaluation of whether the current cycle is targeted to configuration space of a secondary P—P bridge . A positive evaluation requires configuration-address register (as reflected by contents of mirror register ) to have a value indicating that configuration space is enabled and has a value that is currently pointing to the configuration registers of secondary P—P bridge . A positive evaluation also requires the captured cycle to be a read or write host bus cycle targeted to the configuration-data register . A positive evaluation in step results in intercepting step being entered to route the current host bus cycle to configuration registers which are for secondary virtual P—P bridge , wherein the specific configuration registers accessed are determined by the current contents of mirror register .

Assessing step includes an evaluation of whether the captured host bus cycle is targeted to configuration space of a virtual PCI device . A positive evaluation requires configuration-address register (as reflected by contents of mirror register ) to have a value indicating that configuration space is enabled and a value that is currently pointing to the configuration registers of virtual PCI device . A positive evaluation also requires the captured cycle to be a read or write host bus cycle targeted to the configuration-data register . A positive evaluation in step results in intercepting step being entered to route the current host bus cycle to access the particular host bus configuration register as indicated by the contents of mirror register .

Assessing step includes the evaluation of whether the captured host bus cycle is targeted to memory or I/O address space allocated by a computer program to virtual PCI device . If the specific configuration registers that specify memory or I/O space allocated to virtual PCI device have not been previously set, then the results of this evaluation is always negative. The address space allocated to virtual PCI device , as determined by the current contents of PCI configuration registers , are compared to the captured host bus cycle information. If the target for current host bus cycle is within the address space allocated to virtual PCI device , then step is entered to route the current host bus cycle to the appropriate internal storage as indicated by the address and control signals of the captured host bus cycle.

One skilled in the art will appreciate that functions described herein may be implemented in other physical devices than described while keeping with the sprit of the invention.

Although the present invention is described as being applied to PCI systems, one skilled in the art will appreciate that the methods taught herein may be utilized by any system having a host bus and a peripheral bus (similar to a PCI compliant bus) where advantage is obtained by having a device on coupled to the host bus appear, to computer programs running on a processor in the system, as a residing on a peripheral bus.

BRIEF DESCRIPTION OF DRAWINGS

FIGS. 1A, B show a system configuration in accordance with the present invention.

FIG. 2 shows a more detailed system configuration.

FIG. 3 shows a system with a primary virtual bridge.

FIG. 4 shows a system with a secondary virtual bridge and a primary virtual bridge.

FIGS. 5, A, B show flow charts of method embodiments.

CLAIMS

1. An apparatus, comprising: an interface for directly coupling to a host bus having one or more processors without being shared with a host-to-PCI bridge; a device coupled to the interface to perform one or more functions, said device appearing as a virtual PCI device, logically residing on a PCI bus that is coupled to the host bus through the host-to-PCI bridge, wherein access by the device to the host-to-PCI bridge is only through the host bus; and a monitor circuit coupled to said interface and said device to track host bus cycles initiated by at least one of the processors coupled to the host bus, to identify processor initiated host bus cycles targeted to the virtual PCI device, and to generate one or more control signals to enable the device to respond, as the virtual PCI device, to said one or more of said identified host bus cycles targeted to said virtual PCI device without having to access the host-to-PCI bridge.

2. The apparatus of claim 1, further comprising a first storage coupled to the interface and the monitor circuit to store data associated with host bus read cycles addressed to the virtual PCI device, wherein the data is transferred from the first storage to the host bus during the host bus read cycles without accessing a host interface of the host-to-PCI bridge.

3. The apparatus of claim 2, further comprising a second storage coupled to the interface and the monitor circuit to store data associated with host bus write cycles addressed to the virtual PCI device, wherein the data is transferred from the host bus to the second storage during the host bus write cycles without accessing the host interface of the host-to-PCI bridge.

4. The apparatus of claim 1, further comprising a processor coupled to the interface, the processor capable of initiating one or more host bus cycles on the host bus via the interface.

5. The apparatus of claim 3, further comprising an internal bus to connect the device, the monitor circuit, and the first and second storages to the interface.

6. The apparatus of claim 1, wherein the device is a bridge device coupled to one or more other devices and the device appears as a virtual PCI-PCI bridge logically residing on a PCI bus coupling to the host-to-PCI bridge.

7. The apparatus of claim 1, wherein said identified host bus cycles targeted to said virtual PCI device include host bus cycles targeted to memory address space allocated to said virtual PCI device.

8. The apparatus of claim 1, further comprising a mirror register coupled to said host bus and responsive to one or more of said control signals to receive data from said host bus; wherein said monitor circuit is to further identify host bus write cycles targeted to a configuration-address register; and wherein said monitor circuit is to generate said control signals to receive data from said host bus to store in said mirror register during said host bus cycles identified as targeted to said configuration-address register.

9. The apparatus of claim 1, wherein said identified host bus cycles targeted to said virtual PCI device include host bus cycles to I/O address space allocated to said virtual PCI device.

10. The apparatus of claim 2, wherein said first storage includes a first plurality of configuration registers; and wherein said identified host bus cycles include host bus cycles targeted to configuration space reserved for said virtual PCI device.

11. The apparatus of claim 10, wherein said virtual PCI device resides behind a virtual PCI-to-PCI bridge, wherein said first storage includes a second plurality of configuration registers, and wherein said monitor circuit is to further identify host bus cycles targeted to configuration space allocated to said virtual PCI-to-PCI bridge, and wherein said monitor circuit is to generate said plurality of control signals to transfer one or more said data to said host bus during one or more of said identified host bus read cycles targeted to said configuration space allocated to said virtual PCI-to-PCI bridge.

12. An apparatus, comprising: an interface for directly coupling to a host bus without being shared with a host-to-PCI bridge; a first storage, wherein contents of said first storage specify a first address space allocated to a primary PCI bus; a device coupled to the interface to perform one or more functions, the device appearing as a virtual PCI device, logically residing on a PCI bus coupled to the primary PCI bus, wherein access by the device to the host-to-PCI bridge is only through the host bus; a second storage, wherein contents of said second storage specify a second address space allocated to said virtual PCI device; and a control circuit, coupled to said first and said second storage, wherein said control circuit is to couple to a host bus to track processor initiated host bus cycles and to select host bus cycles to route to said primary PCI bus, wherein said routed cycles are to be selected, based on said contents of said first storage and said second storage, to exclude host bus cycles targeted to said second address space.

13. The apparatus of claim 12, wherein said first and said second address space includes memory host bus address space.

14. The apparatus of claim 12, wherein said first and said second address space includes host bus I/O space.

15. The apparatus of claim 12, wherein said first and said second address space includes PCI compliant configuration address space.

16. The apparatus of claim 12, wherein said virtual PCI device is a virtual PCI-to-PCI bridge.

17. The apparatus of claim 16, further comprising: a plurality of configuration registers; a third storage coupled to said control circuit, wherein contents of said third storage indicate a bus and a device number in which said virtual PCI-to-PCI bridge logically resides, and wherein said control circuit is to further select, based on said bus and said device number, host bus cycles, targeted to configuration address space of said virtual PCI-to-PCI bridge, to route to said plurality of configuration registers without having to access a host interface of the host-to-PCI bridge.

18. A system comprising: one or more processors coupled to a host bus; a host-to-PCI bridge coupling a primary PCI bus to the host bus, said host-to-PCI bridge to route processor initiated host bus cycles to the primary PCI bus; and a first host bus device coupled to said host bus and appearing as a first virtual PCI device logically residing on a PCI bus coupled to the primary PCI bus, to monitor said host bus, to identify processor initiated host bus cycles targeted to said first virtual PCI device, and to intercept said identified cycles targeted to said first virtual PCI device without accessing the host-to-PCI bridge, wherein access by the device to the host-to-PCI bridge is only through the host bus; wherein said host-to-PCI bridge does not forward said identified cycles to the PCI bus coupled via the host-to-PCI bridge, which are targeted to said first virtual PCI device.

19. The system of claim 18, wherein said first host bus device includes a plurality of configuration registers, wherein said intercepted cycles, include host bus cycles targeted to configuration space reserved for said first virtual PCI device and are to be routed to access said plurality of configuration registers.

20. The system of claim 18, wherein said first host bus device includes an array of memory devices, wherein said intercepted cycles include host bus cycles targeted to a memory space allocated to said first virtual PCI device and are to be routed to access said array of memory devices.

21. The system of claim 18, further comprising a second host bus device coupled to said host bus, the second host bus device appearing as a second virtual PCI device logically residing on a PCI bus coupled to the primary PCI bus, and the first and second virtual PCI devices having a unique combination of a PCI bus number and device number.

22. The system of claim 18, wherein said first virtual PCI device resides logically behind a primary virtual PCI-to PCI bridge, wherein said primary virtual PCI-to-PCI bridge resides logically behind said primary PCI bus, and wherein said first host bus device is to snoop said host bus to determine a bus number assigned to said primary virtual PCI-to PCI bus.

23. The system of claim 22, wherein said first virtual PCI device resides logically behind a secondary virtual PCI-to PCI bridge which resides logically behind said primary virtual PCI-to-PCI bridge, wherein said first host bus device includes a plurality of bridge configuration registers, and wherein said intercepted cycles include host bus cycles targeted to the configuration space reserved for said secondary virtual PCI-to PCI bridge and are to be routed to access said plurality of bridge configuration registers.

24. A method comprising: capturing a current host bus cycle initiated by a processor coupled to a host bus; determining whether said captured cycle is targeted to a virtual PCI device residing logically at a PCI bus behind a primary PCI bus, the virtual PCI device representing a host bus device directly coupled to the host bus without having to share an interface with a host-to-PCI bridge and without having to access a host interface of the host-to-PCI bridge in order to access the host bus; intercepting said current host bus cycle, if said current cycle is determined to be targeted to said virtual PCI device, without routing said cycle to said primary PCI bus via the host interface of the host-to-PCI bridge; and routing the intercepted host bus cycle to the host bus device without using the host interface of the host-to-PCI bridge to enable the host bus device to respond, as said virtual PCI device, to the host bus cycle.

25. The method of claim 24, wherein said intercepting includes routing to access a storage coupled to said host bus.

26. The method of claim 24, wherein said intercepting includes routing to access a location within a plurality of configuration registers.

27. The method of claim 24, wherein said determining includes determining whether said current cycle is a write cycle targeted to a configuration-address register and snooping said current host bus cycle to receive data from said host bus if said current cycle is a write cycle targeted to said configuration-address register and writing some or all of said data into a mirror register.

28. The methods of claim 24, wherein said determining includes determining whether said current cycle is a write cycle targeted to a location within the configuration registers of a virtual primary PCI-to-PCI bridge in which a bus number is specified; and snooping said current host bus cycle to receive data from said host bus if the current cycle is a write cycle to a location within the configuration registers of a virtual primary PCI-to-PCI bridge in which a bus number is specified and writing said data in a storage.

29. The method of claim 24, wherein said determining includes determining whether said cycle is to a location within the configuration registers of a virtual PCI-to-PCI bridge; and intercepting said current host bus to route to access a location within a plurality of bridge configuration registers if said cycle is to a location within the configuration registers of a virtual PCI-to-PCI bridge.

30. The method of claim 24 wherein said virtual PCI device is a virtual PCI-to-PCI bridge.

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