Method and apparatus for optimal dot product calculation

ABSTRACT

A dot product operator () uses adder trees () of L-1 adders and no multiplication circuits, where L is the length of the parallel dot product operator. Exclusive-or gates provide the function of multiplication by ±1, with the carry-in ports of adders () being used to form the two's complement, resulting in an extremely efficient design in terms of area and power.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE INVENTION

The present invention is best understood in relation to FIGS. 1-4 of the drawings, like numerals being used for like elements of the various drawings.

As stated above, DS-CDMA systems require a correlation operation which can be set forth as:

where the data D(k)=D(k)I+jD(k)Q and pseudo-noise sequence PN(k)=PN(k)I+jPN(k)Q, “*” is the complex conjugate operator and N is the vector length of the complex data and PN vectors D(k)I is the real part of D(k) and D(k)Q is the imaginary part of D(k). D(k)I and D(k)Q are each M bits in width. Similarly, PN(k)I is the real part of PN(k) and PN(k)Q is the imaginary part of PN(k). PN(k)I and PN(k)Q are each one bit in width.

The equation above can be restated as:

where

and i=1, 2, . . . N/L is the number of pieces to finish the whole N length integration and L is the width of the parallel dot product generator.

As stated above; PNI and PNQ are one bit values generated by the LFSR as a stream of “0”s and “1”s. These binary values are generally mapped to and “−1”, respectively. Accordingly, using Ai as an example, if PNI(k)=1(i.e., PNI(k) maps to −1), then PNI(k)DI(k) equals the two's complement of DI(k). The two's complement of an M-bit number DI(k) equals 2M−DI(k) and can also be calculated as the inversion of each bit of DI(k) and adding 1.

An adder tree circuit for calculating Ai, Bi, Ci and Di is shown in FIG. . The adder tree circuit comprises a first level of L exclusive-or gates , individually referenced as exclusive-or gates -. In the illustrated embodiment L=16. Each exclusive-or gate receives an M-bit value for D(k) each bit of D(k) is exclusive-or d with PN(k). The D input and PN input to each gate will depend upon whether Ai, Bi, Ci or Di is being calculated. If Ai is being calculated, the b inputs of the exclusive-or gates will receive DI() through DI(L), for i=1, and the PN inputs of the exclusive-or gates will receive PN1() through PNI(L). FIG. 2 shows an example of one such exclusive-or circuit ; the inputs shown would be for the calculation of Ai where i=1 and k=1.

Returning to FIG. 1, the output of each exclusive-or gate has an M-bit output. Pairs of exclusive-or gates are coupled to the inputs of adders . In the illustrated embodiment, the output of gates and are coupled to the inputs of adder , the output of gates and are coupled to the inputs of adder , the output of gates and are coupled to the input of adder the output of gates and are coupled to the inputs of adder , the output of gates and are coupled to the inputs of adder , the output of gates and are coupled to the inputs of adder , the output of gates and are coupled to the inputs of adder , and the output of gates and are coupled to the inputs of adder , although the addition could be performed in any order. Each adder also receives a carry in of one of the PN bits. In the illustrated embodiment, adder receives bit PN(), adder receives bit PN(), adder receives bit PN(), adder receives bit PN(), adder receives bit PN(), adder receives bit PN(), adder receives bit. PN(), and adder receives bit PN(). Again, as will be discussed in greater detail below, the order of connecting PN bits to carry in ports is not important, so long as each unique PN bit is received by an adder.

A next stage of adders , individually referenced as adders through , receives the outputs of pairs of adders . In the illustrated embodiment, adder receives the M+1 bit outputs from adders and , adder receives the outputs from adders and , adder receives the outputs from adders and , and adder receives the outputs from adders and . Each adder also receives a unique PN bit. In the illustrated embodiment, adder receives bit PN(), adder receives bit PN(), and adder receives bit PN(), adder receives bit PN().

A third stage of adders , individual referenced as adders and , receives the outputs of pairs of adders . In the illustrated embodiment, adder receives the M+2 bit outputs from adders and , adder receives the outputs from adders and . Each adder also receives a unique PN bit. In the illustrated embodiment, adder receives bit PN(), and adder receives bit PN().

In a final stage, adder receives the M+3 outputs of adders and , along with bit PN(). The output of adder is a M+4 bit output. The remaining PN bit which is not connected to a carry-in port of one of the adders - is passed to adders shown in FIG. 3, discussed below.

In operation, the exclusive-or gates perform the (1's complement) multiplication by ±1, depending upon the value &f the associated PN bit. If the PN bit is a “0”, the D bits will pass through the exclusive-or gate unchanged, i.e., D will be multiplied by “1”. If the PN bit is a “1”, the D bits will be inverted.

After the multiplication by ±1 has occurred in the exclusive-or gates , the adders - perform the summation as provided in the equations for Ai, Bi, Ci and Di and also complete the two's complement transformation. As discussed above, forming the two's complement of a number can be done in two steps: (1) inverting the bits of the number and (2) adding a “1” to the inverted bits. The circuit uses the carry-in ports of the various adders - to provided the adding of “1”where appropriate. In cases where the PN bit is equal to “0”, the carry-in will be zero and, therefore, no adding of one will occur. Where the PN bit is equal to “1”, the two's complement conversion requires that the bits of the associated D bits are inverted (performed by the exclusive-or gate ) and a “1” is added at the carry-in port of its associated adder -. Since there are only L-1 adders in the circuit (fifteen in the illustrated embodiment) and L PN bits, one of the PN bits (PN() in the illustrated embodiment) is received by an adder outside of adder tree circuit . (as shown in FIG. ).

FIG. 3 illustrates a circuit for calculating S. Circuit includes four adder tree circuits , individually referenced as circuits , , and , to calculate Ai, Bi, Ci and Di, respectively. Adder tree circuit receives PNI and DI, adder tree circuit receives PNQ and DQ, adder tree circuit receives PNI and DQ, and adder tree circuit receives PNQ, through inverter , and DI. The outputs of these circuits will be Ai, Bi, Ci and Di, with the exception that each output will be off by “1” if the associated PN() is a “1”. The outputs of adder trees and are coupled to the inputs of adder . PN() from adder tree is coupled to the carry-in port of adder . The, outputs of adder trees and are coupled to the inputs of adder . PN() from adder tree is coupled to the carry-in port of adder . The output of adder is coupled to one input of adder . PN() from adder tree is coupled to the carry-in port of adder . The output of adder is coupled to register . The output of register is coupled to one input of AND gate ; the second input of m-bit AND gate is coupled to a ACC_CLEAR (accumulate clear) signal, where m is the bit width of SQ and SI. The output of AND gate is coupled to the other input to adder . The output of register is the SI value. The output of adder is coupled to one input of adder . PN() from adder tree is coupled to the carry-in port of adder . The output of adder is coupled to register . The output of register is coupled to one input of m-bit AND gate ; the second input of AND gate is coupled to the ACC_CLEAR (accumulate clear) signal. The output of AND gate is coupled to the other input to adder . The output of register is the SQ value.

AND Gates and are shown in greater detail in connection with FIG. . Each bit of the SQ output, for AND gate , and each bit of the SI output, for AND gate is coupled to one input of an AND gate ; the other input of each AND gate is coupled to the ACC_CLEAR signal. This is provided to clear the contents of the accumulating registers and .

In operation, the circuit shown in FIGS. 3 and 4 works as follows. Adders and calculate Ai+Bi and Ci+Di, respectively (with the exception of adding PN() bits from adder trees and , which are added into the sum by adders and ). Adders and , along with registers and accumulate the values of Ai+Bi and Ci+Di for N/L cycles to compute SI and SQ.

FIG. 5 illustrates a block diagram of a spread spectrum device incorporating the circuit of FIG. 3. A pseudo-noise generator outputs a sequence of pseudo-noise words PN(k) too circuit along with data steam D(k). Data stream D(k) could be any digital-data stream which would benefit from communication using spread spectrum techniques, such as an analog communication signal, which is translated to a digital signal by A/D (analog to digital) converter , or a native digital signal such as the output of a computing device. The digital data stream D(k) and the pseudo-noise sequence PN(k) are combined to output S, as described above.

The present invention provides significant advantages over the prior art. While a dot product over two vectors generally requires L multiplications and L-1 additions; the present invention does not need expensive multiplier of two's complement numbers as a normal correlator does. By utilizing the carry-in ports of the adders to complete the two's complement operation, a whole level of L M-bit wide adders is saved. Accordingly, gate counts and power consumption are significantly reduced.

For illustration purposes, the circuitry has been shown with specific L and M values, but the circuit could easily expanded or reduced to accommodate L and M values other than those shown. Further, while the implementation has been described for a N with is an integer power of 2, other values of N could be accommodated as well.

Although the Detailed Description of the invention has been directed to certain exemplary embodiments, various modifications of these embodiments, as well as alternative embodiments, will be suggested to those skilled in the art. The invention encompasses any modifications or alternative embodiments that fall within the scope of the claims.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

For a more complete understanding of the present invention, and the advantages thereof, reference is now made to the following descriptions taken in conjunction with the accompanying drawings, in which:

FIG. 1 illustrates a schematic diagram of an adder tree;

FIG. 2 illustrates a schematic diagram of multi-bit exclusive-or circuits used in the adder tree of FIG. 1;

FIG. 3 illustrates a dot product operator circuit;

FIG. 4 illustrates a multi-bit AND gate used in the circuit of FIG. and

FIG. 5 illustrates a spread spectrum device using the dot product operator circuit of FIG. .

CLAIMS

1. A correlator for performing a dot product operation on bits of a pseudo-noise sequence and respective data words of a data stream, comprising: a plurality of inversion circuits, each inversion circuit for selectively inverting bits of a respective data word responsive to the data word's associated pseudo-noise sequence bit; and a binary adder tree comprising a plurality of adders for performing a summation of the outputs of said inversion circuits, each of said adders having a carry-in input coupled to a single respective pseudo-noise sequence bit.

2. The correlator of claim 1 wherein said inversion circuits comprise exclusive-or gates.

3. The correlator of claim 2 wherein said inversion circuits each comprise a plurality of exclusive-or gates, each gate inputting a respective bit of one of said data words and each inputting the associated pseudo-noise sequence bit respective to said data word.

4. The correlator of claim 1 and further comprising an accumulator circuit for accumulating the output of said adder tree.

5. The correlator of claim 4 wherein said accumulator comprises a register coupled to an input and an output of an adder.

6. A correlator for performing a dot product operation on bits of a pseudo-noise sequence and respective data words of a data stream, comprising: a plurality of inversion circuits, each inversion circuit for selectively inverting bits of a respective data word responsive to the data word's associated pseudo-noise sequence bit; a binary adder tree comprising a plurality of adders for performing a summation of the outputs of said inversion circuits, each of said adders having a carry-in input coupled to a single respective pseudo-noise sequence bit; and an accumulator circuit for accumulating the outputs of said adder trees, said accumulator comprising a register coupled to an input and an output of an adder, said adder having a carry-in bit input coupled to one of said pseudo-random sequence bits.

7. A method of performing a dot product operation on bits of a pseudo-noise sequence and respective data words of a data stream, comprising: selectively inverting bits of each data word responsive to its associated pseudo-noise sequence bit; and summing said selectively inverted data words in a binary adder tree comprising a plurality of adders, each of said adders having a carry-in input coupled to a single respective pseudo-noise sequence bit.

8. The method of cairn 7 wherein selectively inverting step comprises the step of performing an exclusive-or operation on each bit of the data word and the bit of the pseudo-random sequence associated with the data word.

9. The method of claim 7 and further comprising accumulating the output of said adder tree.

10. The method of claim 9 wherein said accumulating step comprises storing an accumulated sum in a register for combining with the output of an adder tree.

11. A method of performing a dot product operation on bits of a pseudo-noise sequence and respective data words of a data stream, comprising: selectively inverting bits of each data word responsive to its associated pseudo-noise sequence bit; summing said selectively inverted data words in a binary adder tree comprising a plurality of adders, each of said adders having a carry-in input coupled to a singe respective pseudo-noise sequence bit; and accumulating the outputs of said adder tree, said adder tree comprising a plurality of adders each having a carry-in bit input receiving one of said pseudo-random sequence bits.

12. A spread spectrum device, comprising: circuitry for generating a stream of data words; a pseudo-noise sequence generator for generating a pseudo-noise sequence; and a correlator for performing a dot product operation on bits of said pseudo-noise sequence and respective data words, comprising: a plurality of inversion circuits, each inversion circuit for selectively inverting bits of a respective data word responsive to the data word's associated pseudo-noise sequence bit, and a binary adder tree comprising a plurality of adders for performing a summation of the outputs of said inversion circuits, each of said adders having a carry-in input coupled to a single respective pseudo-noise sequence bit.

13. The spread spectrum device of claim 12 wherein said circuitry for generating a stream of data words includes an analog to digital converter.

14. The spread spectrum device of claim 12 wherein said inversion circuits comprise exclusive-or gates.

15. The spread spectrum device of claim 14 wherein said inversion circuits each comprise a plurality of exclusive-or gates, each gate inputting a respective bit of one of said data words and each inputting the associated pseudo-noise sequence bit respective to said data word.

16. The spread spectrum device of claim 12 and further comprising an accumulator circuit for accumulating the output of said adder tree.

17. The spread spectrum device of claim 16 wherein said accumulator comprises a register coupled to an input and an output of an adder.

18. A spread spectrum device, comprising: circuitry for generating a stream of data words; a pseudo-noise sequence generator for generating a pseudo-noise sequence; and a correlator for performing a dot product operation on bits of said pseudo-noise sequence and respective data words, comprising: a plurality of inversion circuits, each inversion circuit for selectively inverting bits of a respective data word responsive to its the data word's associated pseudo-noise sequence bit; a binary adder tree comprising a plurality of adders for performing a summation of the outputs of said inversion circuits, each of said adders having a carry-in input coupled to a single respective pseudo-noise sequence bit; and an accumulator circuit for accumulating the output of said adder tree, said accumulator comprising a register coupled to an input and an output of an adder, wherein said adder has a carry-in bit input coupled to one of said pseudo-random sequence bits.

19. The correlator of claim 4 wherein said accumulator circuit accumulates the output of said adder tree and the output of at least one additional adder tree.

20. The method of claim 9 wherein said accumulator circuit accumulates the output of said adder tree and the output of at least one additional adder tree.

21. The spread spectrum device of claim 16 wherein said accumulator circuit accumulates the output of said adder tree and the output of at least one additional adder tree.

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