Semiconductor device and method for manufacturing the same

ABSTRACT

The present invention is characterized by including an electrode formed on surface of a semiconductor substrate, wherein said electrode includes a barrier layer consisting of amorphous or microcrystal expressed by the following expression:

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a view showing the structure of ferroelectric capacitor according to the first embodiment out of the present invention.

FIGS. () to () are views showing the manufacturing process of ferroelectric capacitor according to the first embodiment of the present invention.

FIG. 3 is a view describing ferroelectric capacitor according to the first embodiment of the present invention.

FIG. 4 is a SEM picture showing composition ratio of Ta and forming film state according to the second embodiment of the present invention.

FIG. 5 is a SEM picture showing composition ratio of IrTa and forming film state according to the second embodiment of the present invention.

FIG. 6 is a SEM picture showing composition ratio of IrTa and forming film state according to the second embodiment of the present invention.

FIG. 7 is a SEM picture showing composition ratio of IrTa and forming film state according to the second embodiment of the present invention.

FIG. 8 is a SEM picture showing composition ratio of IrTa and forming film state according to the second embodiment of the present invention.

FIG. 9 is a SEM picture showing composition ratio of IrTa and forming film state according to the second embodiment of the present invention.

FIG. 10 is a SEM picture showing composition ratio of Ir and forming film state according to the second embodiment of the present invention.

FIG. 11 is a view showing the structure of semiconductor device according to the third embodiment of the present invention.

FIG. 12 is a view showing relation of annealing temperature and sheet resistance of the semiconductor device.

FIG. 13 is a view showing the structure of semiconductor device according to the fourth embodiment of the present invention.

FIG. 14 is a view showing the structure of ferroelectric memory according to the fifth embodiment of the present invention.

FIGS. () to () are views showing the results measuring hysteresis characteristic of ferroelectric memory according to the fifth embodiment of the present invention.

FIG. 16 is a view showing relation of composition of IrTa and peak value.

FIG. 17 is a view showing the conventional ferroelectric memory.

FIG. 18 is a view describing the conventional ferroelectric memory.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

FIG. 1 shows a structure of a dielectric capacitor according to a first embodiment of the present invention.

The dielectric capacitor according to a first embodiment of the present invention comprises a lower electrode consisting of Ir layer of 100 nm thickness formed on a tungsten plug of the conventional dielectric capacitor and a ferroelectric layer consisting of PZT of 210 nm thickness, and it is characterized in that said lower electrode further has a barrier layer consisting of Ir0.4Ta0.6 of 100 nm thickness at the tungsten plug side as shown in FIG. .

That is, in the present invention, after forming oxide silicon layer on a silicon substrate with the desired element domain, a contact hole is formed on a silicon substrate as shown in FIG. ().

After forming Ti layer and TiN layer not shown, tungsten is buried in the contact hole by CVD method using WF6 as shown in FIG. () so as to form the tungsten plug .

As shown in FIG. (), the barrier layer consisting of Ir0.4Ta0.6 of 100 nm thickness is formed by spattering method.

After this, the lower electrode consisting of Ir layer of 100 nm thickness by spattering method as shown in FIG. ().

After patterning said barrier layer and lower electrode , the PZT thin film is formed on the upper layer by solge method as shown in FIG. (). Ferroelectric layer is formed through crystallization anneal process of 625° C. one minute by rapid thermal annealing (RTA) method.

Finally, an upper electrode is formed so as to complete ferroelectric memory.

According to such the structure, a ferroelectric memory stable and high in reliability is completed without increase in sheet resistance of the lower electrode.

There is not any oxidation of W and IrTa nor peeling-off of film after the annealing process, and it becomes possible to obtain a ferroelectric memory high in reliability.

Since the ferroelectric memory formed by such the way is constructed by amorphous Ir0.4Ta0.6 at the barrier layer , oxygen in ferroelectric layer is obstructed to penetrate at the barrier layer as shown in FIG. .

Therefore, it becomes possible to form a ferroelectric memory having no current leakage and being long life and high in reliability.

Sheet resistance value of laminated body of amorphous Ir0.4Ta0.6 layer of 100 nm thickness and Ir layer of 100 nm thickness is 1×10−1 Ω, and this is no problem as material for electrode.

Because Ir is a cylindrical crystal, the ferroelectric film formed on the upper layer thereof has very good orientation. Although a little amount of oxygen in the ferroelectric film penetrates through Ir, oxygen having penetrated deposits around the cylindrical crystal as IrO2 so as to raise barrier performance. On the other hand, because amorphous Ir0.4Ta0.6 layer is further in barrier performance, oxygen in the ferroelectric film does not penetrate to the substrate side by existence of these two layer films (the Ir layer and the amorphous Ir0.4Ta0.6 layer ).

Thus, ferroelectric performance of the ferroelectric film improves drastically.

Although the amorphous Ir0.4Ta0.6 layer is formed only on the lower electrode in said embodiment, penetration of oxygen in the ferroelectric film is surely prevented by forming the amorphous Ir0.4Ta0.6 layer on the upper electrode as well. However, effect of some degree can be obtained by only either of them. Further, IrTaPt layer, comprising IrTa and additive Pt, is also effective.

The above-mentioned ferroelectric capacitor can be used as a nonvolatile memory by connecting one side of source-drain of a transistor and an upper or lower electrode. Further, it is needless to say that the above mentioned capacitor is applicable for a nonvolatile memory of FET structure using ferroelectric film sandwiched between electrodes as an electrode.

Next, composition of IrxTa1-x will be described as a second embodiment of the present invention. The rest of the structures are similar to those in fore-mentioned first embodiment.

Varying composition ratio x of Ir, IrxTa1-x layer is formed on a silicon substrate by reactive spattering method. The forming film conditions are shown in the following table.

Crystal performance of film and film performance obtained by the result is shown in the following table.

Further, SEM pictures of this time are shown in FIGS. 4 to . Here, in FIGS. 4 to , Ta and IrxTa1-x (X=0.2, 0.4, 0.5, 0.6, 0.8: Ir0.2Ta0.8Ir0.4Ta0.6Ir0.5Ta0.5Ir0.6Ta0.4Ir0.8Ta0.2) are formed on surface of oxide silicon film through silicon film, and in FIG. 10, iridium is formed on surface of oxide silicon film. A part at boundary shown white in the picture is a silicide.

Amorphous state is obtained when content of iridium is 20 to 50% from the result of XRD and the above-mentioned SEM. When content of iridium is 60 to 80%, microcrystal state is obtained. According to the result of SEM, when content of iridium is 40%, it is known that there is not crystal grain and the best amorphous state is obtained.

Amorphous state gives better barrier performance. This is because oxygen permeation (diffusion) is most part permeation in crystal boundary, so that amorphous state gives higher performance in anti-diffusion effect.

On the other hand, with regard to ferroelectric film which is formed above this barrier layer, employing microcrystal for barrier layer makes it possible to obtain better orientation, if microcrystal composing a barrier layer can be orientated.

Next, as a third embodiment of the present invention, resistivity after annealing are measured varying composition of barrier layer in each case of iridium and platinum as an electrode, respectively.

First, a titanium layer of 40 nm thickness of film and a titanium nitride layer of 80 nm of film thickness are formed on surface of a silicon substrate as adhesive above oxide silicon as shown in FIG. . On an upper layer thereof, a tungsten film of 800 nm thickness of film is formed, and thereon amorphous Ir0.4Ta0.6 layer of 100 nm thickness as a barrier layer is formed so that an electrode consisting of iridium layer of 100 nm thickness.

After forming film with the structure, in order to observe resistivity change by oxidation of barrier material after thermal treatment, sheet resistances at each temperature are measured by varying annealing temperature, annealing at an interval of 50° C. from 625° C. by RTA after oxide annealing of 400° C., 30 minutes using a horizontal furnace. The result of the measurement is shown in FIG. 12 with the curve a. Cross-section observation by SEM is carried out to observe oxidation of W and IrTa, and state of film peeling-off after annealing.

As the result, it is known that there is no increase of sheet resistance to about 700° C. and sheet resistance is kept excellently without oxidation of tungsten. At 775° C., peeling-off appears. Although oxidation of IrTa is seemed to start a little at 675° C., oxidation of W is depressed to 700° C. At 775° C., peeling-off appears.

Next, changing amorphous Ir0.4Ta0.6 layer of 100 nm thickness of film, as a barrier layer to amorphous Ir0.5Ta0.5 layer, the rest is formed similarly with the above and then similar measurement is carried out. The result is shown with the curve b.

As a result, in the above-mentioned structure, oxidation of IrTa starts a little at RTA 625° C., and oxidation of W occurs at 775° C.

Further, using amorphous Ir0.4Ta0.6 layer of 100 nm thickness of film as a barrier layer , forming platinum layer of 100 nm thickness of film as an electrode , later process is formed as similar as the above and then similar measurement is carried out. The result is shown with the curve c.

As a result, in the above-mentioned structure, oxidation of IrTa starts a little at RTA 625° C., and oxidation of W occurs at 775° C. Because barrier performance of iridium itself is higher than platinum in the structure of the above-mentioned a, oxidation of IrTa starts a little at RTA 625° C.

Further as comparison example, forming oxide iridium IrO2 layer of 100 nm thickness of film as a barrier layer , using iridium and platinum of 100 nm thickness of film each for an electrode , later process is formed as similar as the above and then similar measurement is carried out for each of iridium and platinum electrode . The result is shown with the curves d and e.

As the result, in the above-mentioned structure, IrTa is oxidized a little and expanded at RTA 725° C., and peeling-off occurs at the boundary of W.

From the above comparison, oxidation of tungsten can not be stopped at step of RTA 625° C. when oxide iridium is used for the barrier layer. It is known by SEM observation that oxidation of IrTa itself occurs from RTA 625° C. though there is no change of sheet resistance in IrTa.

Further it is known that iridium is higher in oxygen barrier performance and better oxygen barrier effect is obtained by using iridium than platinum for the electrode.

Although oxide iridium is formed on the surface, excellent barrier effect can be obtained because resistivity of the oxide iridium is low and oxygen barrier performance is very high.

Next, a fourth embodiment of the present invention will be described. Since oxidation of the barrier layer itself can not be prevented in said third embodiment, a structure able to prevent oxidation of the barrier layer itself will be described.

As shown in FIG. 13, making the thickness of film of the barrier layer half to form amorphous Ir0.4Ta0.6 layer of 50 nm thickness of film, on the upper layer thereof, amorphous Ir0.2Ta0.8 layer of 50 nm thickness of film is laminated so as to be a barrier layer of double construction. A platinum layer of 100 nm thickness of film is used for an electrode. Another construction is formed similarly with said third embodiment.

Resistivity after annealing is measured. As the result, it is known that oxidation of the barrier layer occurs a little at RTA 675° C. and oxidation of tungsten starts.

Next, varying composition of the upper side layer of the double barrier structure, the similar measurement is carried out. That is, making thickness of film of the barrier layer half to form amorphous Ir0.4Ta0.6 layer of 50 nm thickness of film, on the upper layer thereof, a barrier layer of double structure laminating amorphous Ir0.2Ta0.8 layer of 50 nm thickness of film and a barrier layer of double structure forming amorphous IrO2 layer of 50 nm thickness of film at upper side are formed.

As the result, it is known that oxidation of W occurs at RTA 625° C.

In Pt/Ir0.8Ta0.2/Ir0.4Ta0.6/W structure, oxidation of Ir0.4Ta0.6 starts at RTA 625° C. and oxidation of W occurs at RTA 675° C.

Further, in Pt/Ir0.2Ta0.8/Ir0.4Ta0.6/W structure, oxidation of Ir0.2Ta0.8 and Ir0.4Ta0.6 starts at RTA 675° C. and oxidation of W occurs at RTA 725° C.

Therefore, when Ir0.2Ta0.8 is laminated in the structure, it is known that barrier effect is high. It becomes possible to keep good characteristic without oxidation of tungsten at low temperature process of less than 625° C.

Although an electrode with barrier layer is explained in each of fore-mentioned embodiments of second through fourth, an electrode of the present invention is effective and provide an electrode with low resistance and high reliability in the following cases as well: in a-case wherein a layer of ferroelectric or dielectric with high dielectric constant is formed above to form a capacitor, or in a case where a high temperature processing process is included in later processing when forming devices such as electro-luminescence (EL) element, etc.

Next, a fifth embodiment of the present invention will be described. In this example, forming a barrier layer in three layer structure, using a platinum layer of 100 nm thickness of film for an electrode , a ferroelectric layer consisting of PZT layer is formed. Here, in order to resist RTA of 740° C., the following three layer structure is formed: a first barrier layer consisting of IrO2 as a barrier agaist oxygen passing through an electrode consisting of Pt; Ir layer added as a second barrier to barrier oxygen passing through IrO2 or oxygen from the Iro2 itself; and a third barrier layer , as which IrTa is used, serving as a bonding layer of Ir and W (tungsten plug layer ).

That is, as shown in FIG. 14, a barrier layer of three layer structure is formed in which the first barrier layer consisting of IrO2 layer of 65 nm thickness of film, the second barrier layer consisting of iridium layer of 50 nm thickness of film, and the amorphous Ir0.4Ta0.6 layer of 50 nm thickness of film are laminated from the electrode side consisting of platinum layer. The structure of the substrate is formed as similarly as said third embodiment.

Next, a method for manufacturing a ferroelectric capacitor using electrode structure according to the fifth embodiment of the present invention.

First, thermal oxidation is carried out at surface of the silicon substrate , and an oxide silicon layer is formed. Here, thickness of the oxide silicon layer is made 600 nm.

Next, using titanium for target, a titanium layer of 40 nm thickness of film and a titanium nitride layer of 80 nm thickness of film are formed by reactive spattering.

Then, a W layer is formed by CVD method using WF6.

After that, a third barrier layer consisting of amorphous Ir0.4Ta0.6 layer of 50 nm thickness of film is formed by reactive spattering method, on upper layer thereof a second barrier layer consisting of iridium layer of 50 nm thickness of film is formed, on upper layer thereof a first barrier layer consisting of IrO2 layer of 65 nm thickness of film, and further on upper layer thereof an electrode consisting of platinum layer of 100 nm thickness.

Next, PZT film is formed for ferroelectric layer on the (lower) electrode by Sol-Gel method. As starting material, mixed solution of Pb(CH3COO)2.3H2O, Zr(t-OC4H9)4, Ti (i-OC3H7)4 is used. After spin-coating the mixed solution, drying it at 150° C., temporary burning is carried out for 30 seconds at 400° C. in dry air atmosphere. After repeating it 5 times, thermal treatment of 400° C., 30 minutes is carried out in O2 atmosphere. A ferroelectric layer consisting of PZT layer of 210 nm thickness is formed by carrying out crystallization anneal of RTA 740° C. Here, in PbZrxTi1-x, PZT film is formed placing 0.52 for x (indicated PZT (52·48) hereafter).

Further, Ir layer and IrO2 layer are formed on the ferroelectric layer by reactive spattering so as to use as an upper electrode (not shown) of double structure. Here, thickness thereof is formed in 200 nm. Thus, a ferroelectric capacitor is obtained.

In the ferroelectric capacitor formed such way, oxidation of the tungsten plug does not appear, and oxidation of each layer does not appear.

The result of measured hysteresis characteristic of ferroelectric capacitor (PZT(210 nm)/Pt(100 nm)/IrO2(65 nm)/Ir(50 nm)/Ta(50 nm)/W(10 nm)) is shown in FIG. (). For comparing, four structures are formed by varying composition of barrier layer without varying the electrode, the ferroelectric layer, and the substrate layer.

That is, the result of measured hysteresis characteristic of ferroelectric capacitor about the following structures are shown in FIGS. () to (): the second structure; PZT (210 rim)/Pt (100 nm)/IrO2 (65 nm)/Ir (50 nm)/Ir0.4Ta0.6 layer (50 nm)/W (100 nm), the third structure; PZT (210 nm)/Pt (100 nm)/Iro2 (65 nm)/Ir (50 nm)/Ir0.4Ta0.6 layer (50 nm)/W (100 nm), the fourth structure; PZT (210 nm)/Pt (50 nm)/IrO2 (65 nm)/Ir (50 nm)/Ir0.4Ta0.6 layer (50 nm)/W (100 nm), the fifth structure; PZT (210 nm)/Pt (100 nm)/IrO2 (65 nm)/Ir (25 nm)/Ir0.4Ta0.6 layer (50 nm)/W (100 nm). For comparing, hysteresis characteristic of ferroelectric capacitor formed not on the tungsten plug but on oxide silicon layer is shown in FIG. ().

Although in all cases, oxidation of IrTa appears a little, good hysteresis characteristic can be obtained in all cases. Peeling-off appeared at a part where thickness of film of the first barrier layer is thin.

Since crystallization anneal temperature is high, 745° C., it is known that any of them is used practically though oxidation appears a little.

About remanence, it is clear that depletion of Pr is improved considerably. Especially, when IrTa barrier layers are formed on both of the upper electrode and the lower electrode, it is clear that there is hardly any depletion till 100 cycles.

By the way, although IrTa is amorphous, the ferroelectric film formed on surface thereof, too, orientates well by forming a platinum layer on the upper layer.

Instead of the platinum layer, conductive layer good in orientation such as iridium, alloy of platinum and iridium, etc. may be provided. Especially, alloy of platinum and iridium can select grid constant by varying compounding ratio, and this grid constant can be matched easily to that of ferroelectric layer.

Although two layers structure film of titanium layer and titanium nitride layer are used as a bonding layer in the above-mentioned embodiment, any material improving bondability may be used. For example, platinum layer may be used.

Next, peak characteristic greatly changes by varying a little composition ratio of IrTa as shown in FIG. . Therefore, it is possible to obtain suitable characteristic by adjusting a little composition ratio.

Although PZT is used as a ferroelectric film in the above-mentioned each embodiment, any material being oxide ferroelectric may be used. For example, Ba4Ti3O12 and SrBi2Ta2O9 may be used.

It is effective that a dielectric layer having high dielectric constant is used instead of the ferroelectric layer as a capacitor according to another embodiment of the present invention. A lower electrode of platinum including the barrier layer of the present invention is provided on the tungsten plug formed on the oxide silicon layer , and thereon thin film of high dielectric constant having perovskite structure of SrTiO3 and (Sr, Ba) TiO3 is formed as dielectric layer. In this case too, dielectric is improved as similarly as ferroelectric. That is, it is clear that matters described about ferroelectric layer are applicable for dielectric layer having high dielectric constant.

Although ferroelectric capacitor is described in said embodiment, it is needless to say that the present invention is applicable for another process such as wiring passing through high temperature process without limiting to the capacitor.

As described above, according to the present invention, a barrier layer consisting of amorphous or microcrystal is included as an electrode being expressed by the following expression:

M1xM21-x (0

M1: Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, Cr

M2: Ta, Ti, Zr, Hf, W, Y, Mo, Nb

The barrier effect is large so as to prevent mutual diffusion of oxygen etc. and spike because the barrier layer consisting of the amorphous or microcrystal does not have clear grain boundary. Therefore, escape of oxygen from dielectric layer can be prevented so as to depress aging dielectric characteristic. Dielectric thin film formed on the amorphous or microcrystal is good in orientation performance so as to be possible to provide dielectric structure high in reliability.

CLAIMS

1. A semiconductor device having an electrode formed on a surface of a semiconductor substrate, wherein said electrode includes a barrier layer consisting of amorphous or microcrystal expressed by an expression of M1xM21-x(0<x<1), where M1 is selected from a group consisting of Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, and Cr, and M2 is selected from a group consisting of Ta, Ti, Zr, Hf, W, Y, Mo, and Nb.

2. A semiconductor device according to claim 1, wherein composition ratio of said barrier layer is determined so that grain boundary becomes amorphous to an extend such that at least any one of diffusion of oxygen and spike can be prevented.

3. A semiconductor device according to claim 1, wherein said surface of semiconductor substrate is a tungsten plug formed on the semiconductor substrate.

4. A semiconductor device according to claim 1, wherein said surf ace of semiconductor substrate is formed by material which promotes oxidation at crystallization temperature of a dielectric layer to be formed on said surface of semiconductor.

5. A semiconductor device according to claim 1, wherein said surface of semiconductor substrate is formed by at least one kind of polysilicon, tungsten, cobalt, molybdenum, copper, silicide of these, and alloy of these.

6. A semiconductor device according to any one of claims 1 to 5, wherein a dielectric layer is formed on said surface of electrode.

7. A semiconductor device according to claim 6, wherein said dielectric layer is PZT.

8. A semiconductor device comprising: a lower electrode formed on a semiconductor substrate; a dielectric layer formed on said lower electrode and constructed by ferroelectric or dielectric having high dielectric constant; and an upper electrode formed on said dielectric layer, wherein said lower electrode includes a barrier layer consisting of amorphous or microcrystal expressed by an expression of M1xM21-x (0<x<1), where M1 is selected from a group consisting of Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, and Cr, and M2 is selected from a group consisting of Ta, Ti, Zr, Hf, W, Y, Mo, and Nb.

9. A semiconductor device according to claim 8, wherein said barrier layer consists of iridium tantalum layer IrxTa1-x (0<x<1).

10. A semiconductor device according to claim 8, wherein said barrier layer includes a grading layer in which a composition ratio is changed.

11. A semiconductor device according to claim 8, wherein said barrier layer consists of iridium tantalum layer IrxTa1-x (0<x<1) and material of said electrode is iridium.

12. A semiconductor device according to claim 8, wherein said barrier layer consists of iridium tantalum layer IrxTa1-x (0<x<1) and material of said electrode is platinum.

13. A semiconductor device comprising: a lower electrode formed on a semiconductor substrate; a dielectric layer formed on said lower electrode and constructed by ferroelectric or dielectric having high dielectric constant; an upper electrode formed on said dielectric layer; and a barrier layer formed between said dielectric layer and said upper electrode, consisting of amorphous or microcrystal expressed by an expression of M1xM21-x (0<x<1), where M1 is selected from a group consisting of Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, and Cr, and M2 is selected from a group consisting of Ta, Ti, Zr, Hf, W, Y, Mo, and Nb.

14. A semiconductor device according to claim 13, wherein said barrier layer consists of iridium tantalum layer IrxTa1-x (0<x<1).

15. A semiconductor device having an electrode formed on a surface of a semiconductor substrate, wherein said electrode is constructed by amorphous or microcrystal single layer expressed by an expression of M1xM21-x (0<x<1), where M1 is selected from a group consisting of Au, Pt, Ir, Pd, Os, Re, Rh, Ru, Cu, Co, Fe, Ni, V, and Cr, and M2 is selected from a group consisting of Ta, Ti, Zr, Hf, W, Y, Mo, and Nb.

16. A semiconductor device according to claim 1, wherein said barrier layer includes of constructive element of substrate material.

17. A semiconductor device having an electrode formed on a surface of a semiconductor substrate, wherein said electrode includes an amorphous or microcrystal barrier layer made of IrTaPt.

18. A semiconductor device according to claim 1, wherein M1 contains Ir and M2 contains Hf.

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