Nonvolatile memory structures and fabrication methods

ABSTRACT

To fabricate a semiconductor memory, one or more pairs of first structures are formed over a semiconductor substrate. Each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells. The control gates overlie the floating gates. Each pair of the first structures corresponds to a plurality of doped regions each of which provides a source/drain region to a memory cell having the floating and control gates in one or the structure and a source/drain region to a memory cell having floating and control gates in the other one of the structures. For each pair, a second conductive line is formed whose bottom surface extends between the two structures and physically contacts the corresponding first doped regions. In some embodiments, the first doped regions are separated by insulation trenches. The second conductive line may form a conductive plug at least partially filling the region between the two first structures.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DESCRIPTION OF PREFERRED EMBODIMENTS

The description of the preferred embodiments is illustrative and not limiting. The invention is not limited by any particular dimensions, materials, processing steps, doping levels, crystal orientation, layer thicknesses, layouts, or any other features, unless expressly stated otherwise.

FIG. 9A is a top view of a flash memory array of self-aligned triple-gate memory cells . FIG. 9B illustrates a cross section of the array along the line B—B in FIG. A. FIG. 9C illustrates a cross section along the line C—C in FIG. A. FIG. 10A is a circuit diagram of the array. FIG. 10B is a top view illustrating some additional features.

In FIGS. 9A, A, B, bitlines extend horizontally. The bitlines are formed from a conductive layer overlying the memory cells (for example, aluminum or tungsten, not shown in FIGS. 9B, C). The bitlines contact the memory cells' bitline regions in contact regions . Source lines S extend vertically between the adjacent row structures . The source lines S physically contact the memory cells' source line regions . Each row structure includes a conductive control gate line (e.g. doped polysilicon) extending vertically and providing control gates for a row of memory cells. Floating gates (made of doped polysilicon, for example) underlie the control gates . Each floating gate extends between adjacent isolation trenches . Trenches extend horizontally between the bitlines .

Each structure is a self-aligned stack.

Conductive wordlines W (e.g. doped polysilicon) are perpendicular (or at some other angle) to the bitlines. Each wordline W provides select gates for a row of memory cells. Each wordline W is a self-aligned sidewall spacer formed over a sidewall of a corresponding stack . Wordlines W are insulated from the adjacent control gates and floating gates by silicon nitride spacers and silicon dioxide . Layers , can be formed without a mask.

As shown in FIG. 10A, each row of memory cells has two cells between each two adjacent bitlines . Each row has a control gate line and a wordline W. Two adjacent memory rows share a source line . In each memory cell , an NMOS select transistor S and a floating gate transistor F are connected in series. The gate of the select transistor S is provided by wordline W. The control gate of the transistor F is provided by line .

Each cell can be erased by Fowler-Nordheim tunneling of electrons from its floating gate (FIG. 9B) through silicon dioxide to source line region or substrate region . (Region contains the channel regions of the memory cells.) The cell can be programmed by source-side hot electron injection. The term “source-side hot electron injection” assumes that a cell's bitline region is called a “source”. At other times, this region is called a drain, and the source line region is called a source. Each of regions , may also be called a source/drain region. The invention is not limited by any particular terminology.

The beginning fabrication stages for one embodiment of the memory of FIGS. 9A-10B are identical to the respective fabrication stages of a memory described in U.S. patent application Ser. No. 09/640,139 filed on Aug. 15, 2000 by H. T. Tuan et al., entitled “Nonvolatile Memory Structures and Fabrication Methods” (now U.S. Pat. No. 6,355,524), incorporated herein by reference. More particularly, the memory can be formed in and over an isolated P-type region of monocrystalline silicon substrate (FIG. ). In one embodiment, region is formed as follows. N type dopant is implanted into substrate by ion implantation through a mask opening to form an N-region which insulates the region from below. In a separate ion implantation step or series of steps, using another mask (not shown), N type dopant is implanted to form an N-region completely surrounding the region on all sides. In some embodiments, this step creates also N wells (not shown) in which peripheral PMOS transistors will be formed for peripheral circuitry. Such circuitry may include sense amplifiers, input/output drivers, decoders, voltage level generators.

Regions , are at a voltage equal to or above the voltage of substrate region during memory operation. The areas of substrate that surround the regions , are at some voltage equal to or below the voltage of the regions , . In some embodiments, the regions , , are shorted together, and the region is at ground.

The invention is not limited to a particular region isolation technique, or to memories having an isolated substrate region.

As shown in FIG. 12A, silicon dioxide (tunneling oxide) is grown on substrate by thermal oxidation. In some embodiments, the oxide is grown to a thickness of 9 nm.

Conductive polysilicon layer is formed on oxide . In some embodiments, polysilicon is deposited to a thickness of nm by LPCVD (low pressure chemical vapor deposition), and is lightly doped (N type) during or after deposition. Layer will provide the floating gates and, possibly, other circuit elements as needed for the peripheral circuitry. Such elements may include interconnects, transistor gates, resistors, capacitor plates.

Silicon nitride is deposited over polysilicon . In some embodiment, nitride is deposited to a thickness of 120 nm by LPCVD.

Photoresist mask is formed photolithographically over nitride . Nitride and polysilicon are etched through the mask openings to form strips extending in the bitline direction through the memory array. In the top view of FIG. 12B, the “BL” axis indicates the bitline direction. The “WL” axis indicates the wordline direction.

A misalignment of mask does not affect the cell geometry and hence may have to be accommodated, if at all, only at the array boundaries and in the peripheral areas (the areas in which the peripheral circuitry is located).

After the polysilicon etch, oxide and substrate region are etched through the openings in mask to form isolation trenches (FIG. ). Isolation trenches for the peripheral circuitry (not shown) are also formed in this step. In some embodiments, the trench depth is 0.25 μm.

Then mask is removed.

Whenever a masked etch of two or more layers is described herein, it is assumed, unless stated otherwise, that only the top layer may be etched using the mask. After the top layer is etched, the mask may be removed, and the remaining layers may be etched with the top layer as a mask, or even without a mask. For example, after the etch of nitride , the mask may be removed, and then polysilicon , oxide and substrate can be etched with nitride as a mask. Nitride may also be etched but is not completely removed.

Trench insulation (FIG. 13) fills the trenches and covers the wafer. In some embodiments, insulation is formed as follows. A 13.5 nm layer of silicon dioxide is grown on the exposed surfaces of trenches by a well-known RTO (rapid thermal oxide) process. Then a 480 nm layer of silicon dioxide is deposited by chemical vapor deposition (CVD) using high density plasma (HDP).

Trench insulation is subjected to chemical mechanical polishing (CMP) and/or some blanket etch process, until silicon nitride is exposed (FIG. ). Nitride acts as a stop layer during this step. Then nitride is removed (by a wet etch, for example). Optionally, insulation is etched down also. The resulting structure may have a planar top surface as shown in FIG. . Alternatively, the etch of insulation may expose the sidewalls of polysilicon . This may improve the efficiency of the memory cells, as explained in the aforementioned U.S. patent application Ser. No. 09/640,139.

Then insulation is formed. See FIGS. 9B, C, A, B. FIGS. 16A, B show memory array cross sections by planes parallel to the bitlines. In FIG. 16A, the cross section is taken between trenches . In FIG. 16B, the cross sectional plane passes through a trench .

Similarly, FIGS. 17A, A, A, A, , A, illustrate cross sections taken between the trenches. FIGS. 17B, B, B, B, B illustrate cross sections taken along a trench .

In some embodiments, the insulation is ONO (oxide-nitride-oxide).

Layer is formed on insulation . In some embodiments, layer is polysilicon deposited by LPCVD and doped N+ or P+ during or after deposition. In other embodiments, layer is polysilicon covered by tungsten suicide. Other conductive materials can also be used.

A photoresist layer (not shown) is deposited and patterned photolithographically into a mask that contains strips extending in the wordline direction over the memory array. This mask defines stacks (FIGS. 9A, B, C, A, B). This mask can also be used to pattern the polysilicon and silicon nitride in the peripheral areas (not shown) as described in the aforementioned U.S. patent application Ser. No. 09/640,139. Layer may provide transistor gates, interconnects, and other features in the peripheral areas. A misalignment of this resist mask does not change the geometry of the memory cells and hence may have to be accommodated only at the boundaries of the memory array and in the peripheral areas.

Layers , , , , are etched to define the stacks . The resulting memory array cross sections are shown in FIGS. 16A, B.

The structure is oxidized (e.g. by RTO, i.e. rapid thermal oxidation). As a result, silicon dioxide (FIGS. 17A, B) is grown on the exposed surface of substrate region to a thickness of 5 nm. This operation also results in oxidation of the exposed sidewalls of polysilicon layers , . The horizontal thickness of oxide on the polysilicon sidewalls is 8 nm.

A thin conformal layer of silicon nitride (FIGS. 18A, B) is deposited to a 20 nm thickness by LPCVD. Layer is etched anisotropically without a mask to form spacers over the sidewalls of stacks .

This etch also removes exposed portions of oxide . Silicon dioxide is regrown on substrate region . This oxide, shown at in FIG. 18A, will provide gate dielectric for the select transistors. An exemplary thickness of oxide is 5 nm.

In some embodiments, either nitride or oxide is omitted.

A conductive layer . (FIGS. 19A, B) is formed over the wafer. In some embodiments, layer . is polysilicon deposited by LPCVD and heavily doped during or after deposition. An exemplary thickness of layer . is 50 to 100 nm. Other thicknesses can also be used.

Photoresist mask is formed over the wafer and patterned photolithographically to expose the areas in which the source line regions will be formed. See also FIGS. 20A, B. In the embodiment of FIGS. 19A, B, the mask exposes regions extending throughout the memory array between two adjacent stacks . The longitudinal edges of mask can be positioned anywhere over the respective stacks , so their positioning is not critical if the mask alignment tolerance is not more than one half of the width of a stack . In some embodiments, the minimal feature size is 0.14 μm. The mask alignment tolerance is 0.07 μm. The width of each stack is 0.14 μm, that is, twice the alignment tolerance.

Polysilicon . and oxide are removed from the areas exposed by the mask. Trench insulation in the exposed areas may be slightly reduced in thickness during the etch of oxide .

After the oxide etch, mask remains in place as N type dopant (e.g. phosphorus) is implanted into the wafer to heavily dope (N+) the source line regions , as shown by arrows in FIG. A. This is a “deep” implant done to enable the source lines to carry high voltages for erase and/or programming operations. The deep implant will also provide a suitable overlap between the doped source line regions and the floating gates when the dopant diffuses laterally (as shown in FIG. A).

In some embodiments, the dopant does not penetrate the insulation , so the bottoms of trenches are not doped (see FIG. B). Whether or not the dopant penetrates the insulation , insulation prevents the dopant from coming close or reaching the N-region (FIG. ). Therefore, a high leakage current or a short between the source lines and the region is avoided. In some embodiments, the top surface of region at the end of fabrication (after thermal steps) is about 1 μm below the top surface of substrate (of region ). The trench depth is 0.25 μm.

Then the resist is removed. Polysilicon . protects the oxide over the bitline regions during the removal of resist and a subsequent wafer cleaning operation.

In some embodiments, the resist is removed before the implant . Polysilicon . acts as a mask during the implant.

In some embodiments, the implant is performed before the etch of polysilicon . or oxide . The implant is performed through the polysilicon or the oxide or both. In some embodiments, layer . is omitted.

Conductive polysilicon layer . (FIG. 21) is formed. In some embodiments, polysilicon . is deposited by LPCVD to a thickness of 300 nm, and is heavily doped during or after deposition. The dopant type (N+ or P+) is the same as for layer .. Layers ., . are subjected to a blanket anisotropic etch (e.g. RIE) to form spacers W over the sidewalls of stacks on the side of the bitline regions (FIGS. 22A, B). Layers ., . are etched off the top of stacks . The vertical thickness of nitride and polysilicon layers ., ., can be adjusted to control the width of the polysilicon spacers.

Polysilicon plugs S formed by polysilicon . fill the gaps between adjacent stacks on the side of source line regions . Each polysilicon plug S forms a source line extending through the memory array and physically contacting the underlying source line regions . The bottom surface of each plug S physically contacts the trench insulation . We will sometimes refer to polysilicon layers ., . collectively as layer .

In addition to the wordlines and source lines, layer can provide interconnects, transistor gates, and other circuit elements for the peripheral circuitry. For that purpose, layer can be masked in the peripheral areas before it is etched. No such masking is needed over the memory array.

In some embodiments, polysilicon . does not entirely fill the regions between adjacent stacks over the source line regions . Polysilicon . may be recessed relative to the top of the stacks . In some embodiments, polysilicon . forms spacers over the sidewalls of stacks over the regions . In this case, a source line S consists of two such spacers shorted together by regions .

A blanket N+ implant (FIG. 23) is performed to dope the bitline regions . Stacks , polysilicon , and trench insulation mask the substrate during this implant. Polysilicon is also implanted during this step.

This implant does not penetrate insulation , so the bitline regions are not shorted together.

Memory fabrication can be completed using known techniques. Insulating layers (not shown) can be deposited. Contact openings such as (FIG. 9A) can be formed. Conductive materials can be deposited and patterned to provide bitlines and other features as needed.

The gates of peripheral transistors can be formed from polysilicon layer or . See the aforementioned U.S. patent application Ser. No. 09/640,139. In some embodiments, some of the peripheral transistor gates or other features are formed using layer , while other peripheral gates or features are formed using layer .

In some embodiments, source lines S are silicided to reduce their resistance. The silicidation can be performed using the source line silicidation techniques described in U.S. patent application Ser. No. 09/640,139.

FIG. 24 illustrates another flash memory array according to the present invention. Each isolation trench extends between adjacent source line regions but does not cross the source line regions. The boundaries of the isolation trenches are shown at B.

This memory can be fabricated as follows. The substrate doping and the trench isolation can be performed as described in U.S. patent application Ser. No. 09/640,139. For example, trenches can be defined by resist (FIG. 12A) or by a combination of resist with another resist layer.

The remaining fabrication steps can be identical to those described above in connection with FIGS. 16A-23.

In some embodiments of FIGS. 9A through 24, a memory cell is programmed (rendered non-conductive) via source-side hot electron injection. See W. D. Brown et al., “Nonvolatile Semiconductor Memory Technology” (1998), pages 21-23.

A memory cell can be erased using Fowler-Nordheim tunneling from floating gate to source line region or to substrate region .

A memory may have multiple memory arrays, each with its own bitlines and wordlines. Different arrays may be fabricated in the same substrate region or in different isolated regions in the same integrated circuit.

The invention is not limited to the embodiments described above. The invention is not limited to any particular erase or programming mechanisms (e.g. Fowler-Nordheim or hot electron injection). The invention covers non-flash EEPROM memories and other memories, known or to be invented. The invention is not limited to the materials described. In particular, control gates, select gates, and other conductive elements can be formed from metals, metal suicides, polycides, and other conductive materials and their combinations. Silicon dioxide and silicon nitride can be replaced with other insulating materials. P and N conductivity types can be interchanged. The invention is not limited to any particular process steps or order of steps. For example, in some embodiments, thermal oxidation of silicon can be replaced with depositing silicon dioxide or some other insulator by chemical vapor deposition or some other technique, known or to be invented. The invention is not limited to silicon integrated circuits. Other embodiments and variations are within the scope of the invention, as defined by the appended claims.

BRIEF DESCRIPTION OF THE DRAWINGS

FIGS. 1-7 are cross section illustrations of a prior art flash memory at different stages of fabrication.

FIG. 8 is a top view of the memory of FIGS. 1-7.

FIG. 9A is a top view of a memory according to some embodiments of the present invention.

FIGS. 9B, C are cross section illustrations of the memory of FIG. A.

FIG. 10A is a circuit diagram of the memory of FIG. A.

FIG. 10B is a top view of the memory of FIG. A.

FIGS. 11, A are cross section illustrations of the memory of FIG. 9A at different stages of fabrication.

FIG. 12B is a top view of the structure of FIG. A.

FIGS. 13-15, A, B, A, B, A, B, A, B, A, B, , A, are cross section illustrations of memory embodiments of the present invention.

FIG. 24 is a top view of a memory embodiment of the present invention.

In the drawings, the reference numbers are used as indicated in the following table. The list of the reference numbers in this table is not exhaustive. The description of the features is not complete, and is not limiting. For example, silicon dioxide can be replaced with other insulators. Not all of the functions described for a reference number have to be present in the invention, and also functions not described can be present.

CLAIMS

1. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure, each first structure having a top surface; forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a first source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a first source/drain region to a memory cell having floating and control gates in the structure S2; wherein for each pair of structures (S1, S2), the structure S1 has a first sidewall facing the structure S2 and has a second sidewall opposite from the first sidewall, and the structure S2 has a first sidewall facing the structure S1 and a second sidewall opposite from the first sidewall; and the method further comprises: for each pair (S1, S2), forming at least one second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S1 and S2 below the top surfaces of the structures S1 and S2 and physically contacts those first doped regions which provide the first source/drain regions to the memory cells having floating and control gates in the structures S1, S2; forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control gates in the first structure, the conductive gates being insulated from the floating and control gates; forming second doped regions in the substrate which provide second source/drain regions to the memory cells of the memory array; and forming bit lines each of which passes across a plurality of the second conductive lines and electrically contacts a plurality of the second doped regions.

2. The method of claim 1 further comprising forming insulation regions recessed into the semiconductor substrate, wherein for each pair of the first structures, the corresponding first doped regions are separated from each other by the insulation regions.

3. The method of claim 2 wherein forming the insulation regions comprises etching trenches in the semiconductor substrate and filling the trenches with insulation.

4. The method of claim 2 wherein the insulation regions are formed before the first doped regions.

5. The method of claim 1 wherein forming a second conductive line comprises forming a conductive layer and etching the conductive layer to form a conductive plug between each pair of structures (S1, S2).

6. The method of claim 5 wherein the etching of the conductive layer results in the third conductive line being formed from the conductive layer over each of the second sidewalls of the structures S1 and S2.

7. The method of claim 6 wherein each third conductive line over the second sidewall of a first structure provides select gates for the memory cells having their control and floating gates in the first structure.

8. The method of claim 7 wherein the conductive layer from which the second and third conductive lines are formed comprises a conductive layer L1 and a conductive layer L2, and forming and etching the conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions; removing the mask, wherein the layer L1 protects an underlying material during the mask removing operation; forming the layer L2; and etching the layers L1 and L2.

9. The method of claim 8 further comprising etching the layer L1 through the opening or openings in the mask before the mask is removed.

10. The method of claim 8 further comprising forming gate dielectric for select transistors of the memory cells before forming the layer L1, the underlying material being the gate dielectric.

11. A method for fabricating a semiconductor integrated circuit comprising a memory array, the method comprising: forming a first insulating layer over a semiconductor substrate; forming a first conductive layer over the first insulating layer; forming a second insulating layer over the first conductive layer; forming a second conductive layer over the second insulating layer; patterning the first and second conductive layers and the second insulating layer to form a plurality of first structures each of which comprises: a plurality of floating gates for a plurality of memory cells, the floating gates being formed from the first conductive layer; and a first conductive line made from the second conductive layer and providing control gates for the memory cells; forming first doped regions in the substrate which provide first source/drain regions to memory cells of the memory array, such that each first structure has a first sidewall adjacent to a plurality of the first doped regions; forming a third conductive layer over the first structures; anisotropically etching the third conductive layer, the etching operation being performed without masking the third conductive layer over the memory array, the etching operation forming, from the third conductive layer: a spacer over a second sidewall of each first structure; one or more second conductive lines each of which extends between adjacent first sidewalls of two first structures and physically contacts the first doped regions to which the adjacent first sidewalls are adjacent; forming an insulator over the spacers and the second conductive lines.

12. The method of claim 11 further comprising forming trenches in the substrate and filling the trenches with an insulator, wherein the first doped regions adjacent to first sidewalls of two given first structures are separated from each other by the trenches.

13. The method of claim 11 wherein the substrate does not provide a conductive path to electrically interconnect the first doped regions adjacent to the first sidewalls of two given first structures.

14. The method of claim 11 wherein each second conductive line forms a conductive plug at least partially filling a region between the first sidewalls of two first structures.

15. The method of claim 11 wherein each second conductive line is a spacer on the first sidewall of one of the first structures.

16. The method of claim 15 wherein the one or more second conductive lines include two spacers on respective two adjacent first sidewalls of two first structures, the spacers being separated from each other.

17. The method of claim 11 wherein the third conductive layer comprises a conductive layer L1 and a conductive layer L2, and forming the third conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions through the mask opening or openings; removing the mask, wherein the layer L1 protects an underlying material during the mask removing operation; and forming the layer L2.

18. The method of claim 17 further comprising etching the layer L1 through the opening or openings in the mask before the mask is removed.

19. The method of claim 17 further comprising forming gate dielectric for select transistors of the memory cells before forming the layer L1, the underlying material being the gate dielectric.

20. The method of claim 11 wherein the third conductive layer comprises a conductive layer L1 and a conductive layer L2, and forming the third conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions; removing the mask; after removing the mask, cleaning a wafer in which the integrated circuit is being formed, wherein the layer L1 protects an underlying material during the cleaning operation; after cleaning the wafer, forming the layer L2.

21. The method of claim 20 further comprising etching the layer L1 through the opening or openings in the mask before the mask is removed.

22. The method of claim 21 further comprising forming gate dielectric for select transistors of the memory cells before forming the layer L1, the underlying material being the gate dielectric.

23. The method of claim 11 further comprising: forming second doped regions in the substrate which provide second source/drain regions to the memory cells of the memory array; and forming bit lines each of which passes across a plurality of the first conductive lines and electrically contacts a plurality of the second doped regions.

24. The method of claim 11 further comprising: forming second doped regions in the substrate which provide second source/drain regions to the memory cells of the memory array, and forming bit lines each of which passes across a plurality of the second conductive lines and electrically contacts a plurality of the second doped regions.

25. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control sates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure, each first structure having a top surface; forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a first source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a first source/drain region to a memory cell having floating and control gates in the structure S2; wherein for each pair of structures (S1, S2), the structure S1 has a first sidewall facing the structure S2 and has a second sidewall opposite from the first sidewall, and the structure S2 has a first sidewall facing the structure S1 and a second sidewall opposite from the first sidewall; and the method further comprises: for each pair (S1, S2), forming at least one second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S1 and S2 below the ton surfaces of the structures S1 and S2 and physically contacts those first doped regions which provide the first source/drain regions to the memory cells having floating and control gates in the structures S1, S2; and forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control gates in the first structure, the conductive gates being insulated from the floating and control gates; wherein two second conductive lines are provided for each pair (S1, S2), each second conductive line being a spacer on the first sidewall of a respective one of the structures S1, S2.

26. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control rates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure, each first structure having a top forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a first source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a first source/drain region to a memory cell having floating and control gates in the structure S2; wherein for each pair of structures (S1, S2), the structure S1 has a first sidewall facing the structure S2 and has a second sidewall opposite from the first sidewall, and the structure S2 has a first sidewall facing the structure S1 and a second sidewall opposite from the first sidewall; and the method further comprises: for each pair (S1, S2), forming at least one second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S1 and S2 below the top surfaces of the structures S1 and S2 and physically contacts those first dosed regions which provide the first source/drain regions to the memory cells having floating and control gates in the structures S1, S2; forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control gates in the first structure, the conductive gates being insulated from the floating and control gates; forming second doped regions in the substrate which provide second source/drain regions to the memory cells of the memory array; and forming bit lines each of which passes across a plurality of the third conductive lines and electrically contacts a plurality of the second doped regions.

27. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control sates in each first structure overlying the floating gates of the first structure, each first structure having a top surface; forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a first source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a first source/drain region to a memory cell having floating and control gates in the structure S2; wherein for each pair of structures (S1, S2), the structure S1 has a first sidewall facing the structure S2 and has a second sidewall opposite from the first sidewall, and the structure S2 has a first sidewall facing the structure S1 and a second sidewall opposite from the first sidewall; and the method further comprises: for each pair (S1, S2), forming at least one second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line extends between the first structures S1 and S2 below the ton surfaces of the structures S1 and S2 and physically contacts those first doped regions which provide the first source/drain regions to the memory cells having floating and control gates in the structures S1, S2; and forming a third conductive line adjacent to the second sidewall of each first structure, the third conductive line providing conductive gates to the memory cells having the floating and control sates in the first structure, the conductive gates being insulated from the floating and control gates; wherein the conductive layer from which the second and third conductive lines are formed comprises a conductive layer L1 and a conductive layer L2, and forming and etching the conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions through the mask opening or openings; removing the mask; after removing the mask, cleaning a wafer in which the integrated circuit is being formed, wherein the layer L1 protects an underlying material during the cleaning operation; after cleaning the wafer, forming the layer L2.

28. The method of claim 27 further comprising etching the layer L1 through the opening or openings in the mask before the mask is removed.

29. The method of claim 27 further comprising forming gate dielectric for select transistors of the memory cells before forming the layer L1, the underlying material being the gate dielectric.

30. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure; forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a source/drain region to a memory cell having floating and control gates in the structure S2; forming a conductive layer, etching the conductive layer to form, for each pair (S1, S2), a second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line physically contacts the first doped regions which provide the source/drain regions to the memory cells having floating and control gates in the structures S1, S2; wherein the conductive layer comprises a conductive layer L1 and a conductive layer L2, and forming and etching the conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions through the mask opening or openings; removing the mask, wherein the layer L1 protects an underlying material during the mask removing operation; forming the layer L2; and etching the layers L1 and L2 to form the second conductive line or lines, each second conductive line comprising a portion of the layer L1 over said underlying material.

31. The method of claim 30 wherein the underlying material protected by the layer L1 is a dielectric formed on the semiconductor substrate.

32. The method of claim 31 wherein the dielectric is a gate dielectric comprising silicon oxide, and the mask comprises photoresist.

33. A method for fabricating a semiconductor integrated circuit comprising a memory, the method comprising: forming one or more pairs of first structures over a semiconductor substrate, wherein each first structure comprises (a) a plurality of floating gates of memory cells and (b) a first conductive line providing control gates for the memory cells, the control gates in each first structure overlying the floating gates of the first structure; forming first doped regions in the semiconductor substrate, wherein each pair (S1, S2) of the first structures corresponds to a plurality of the first doped regions each of which provides (i) a source/drain region to a memory cell having floating and control gates in the structure S1 and (ii) a source/drain region to a memory cell having floating and control gates in the structure S2; forming a conductive layer; etching the conductive layer to form, for each pair (S1, S2), a second conductive line over the semiconductor substrate, wherein a bottom surface of the second conductive line physically contacts the first doped regions which provide the source/drain regions to the memory cells having floating and control gates in the structures S1, S2; wherein the conductive layer comprises a conductive layer L1 and a conductive layer L2, and forming and etching the conductive layer comprises: forming the layer L1; forming a mask over the layer L1, the mask having an opening or openings at a location of the first doped regions; introducing a dopant into the first doped regions through the mask opening or openings; removing the mask; after removing the mask, cleaning a wafer in which the integrated circuit is being formed, wherein the layer L1 protects an underlying material during the cleaning operation; after cleaning the wafer, forming the layer L2; etching the layers L1 and L2 to form the second conductive line or lines, each second conductive line comprising a portion of the layer L1 over said underlying material.

34. The method of claim 33 wherein the underlying material protected by the layer L1 is a dielectric formed on the semiconductor substrate.

35. The method of claim 34 wherein the dielectric is a gate dielectric comprising silicon oxide, and the mask comprises photoresist.

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