Method for fabricating a mask read-only-memory with diode cells

ABSTRACT

A method for fabricating a mask read-only-memory with diode cells is provided. A doped conductive layer with a first conductivity is formed on bit lines. Then, a photoresist layer with a mask ROM pattern is formed on an interlayer dielectric layer on the doped conductive layer for serving as an etching mask, thereby forming openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer. Performing ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each exposed region of the doped conductive layer, so that the doped conductive layer and the diffusion regions formed therein constitute diode cells that are served as memory cells. A contact plug is formed in each opening unto the diode cell and a conductive layer is formed on the contact plug for serving as word lines.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

BRIEF DESCRIPTION OF THE DRAWINGS

The objectives and features of the present invention as well as advantages thereof will become apparent from the following detailed description, considered in conjunction with the accompanying drawings.

FIG. 1A is a schematic top view of a conventional mask ROM;

FIGS. 1B to C are schematic cross-sectional views of various steps for fabricating the conventional mask ROM including a coding process of the mask ROM; and

FIGS. 2A to E are schematic cross-sectional views of various steps for fabricating a mask ROM with diode cells according to one preferred embodiment of the present invention.

DESCRIPTION OF THE EMBODIMENTS

The present invention provides a method for fabricating a mask ROM with diode cells, which uses a structure of a contact plug/a PN diode instead of a channel transistor to serve as a memory cell. The process for forming the structure of the contact plug/PN diode is simple and can provide a well-defined code area even though the device dimension is shrunk down. The manufacturing cost is also reduced. Furthermore, the area of the semiconductor substrate occupied by one PN diode is smaller than that of the channel transistor. Thus, a high-density mask ROM device can be obtained by the present method.

The present method for fabricating a mask ROM with diode cells will be described in detail according to one preferred embodiment of the present invention with reference to the accompanying drawings.

FIGS. 2A to E are schematic cross-sectional views of various steps for fabricating a mask ROM with diode cells according to one preferred embodiment of the present invention. Firstly, referring to FIG. 2A, a semiconductor substrate is provided. The semiconductor substrate can be silicon substrate, germanium substrate, germanium arsenic substrate and the like. Performing an ion implantation process to form a buried diffusion layer with a first conductivity in the top portion of the semiconductor substrate to be served as bit lines. The first conductivity can be N type conductivity or P type conductivity. In the preferred embodiment, the buried diffusion layer is a N+ buried diffusion layer, as shown in FIG. A. Referring to FIG. 2B, then, a doped conductive layer with the first conductivity is formed on the buried diffusion layer . The doped conductive layer is preferably an N− doped polysilicon layer, which can be formed by an in-situ doped low pressure chemical vapor deposition (LPCVD) method with a reaction gas of SiH4 and a dopant source of PH3 at a temperature of about 600-650° C. and under a pressure of about 0.3-0.6 torr. Alternately, the N− doped polysilicon layer can be formed by a post-LPCVD thermal diffusion method at a temperature of about 900° C. to drive in dopant source, such as arsenic and POCl3, to the polysilicon layer formed on the buried diffusion layer . Besides, the N− doped polysilicon layer can be formed by an ion implantation process with dopant source, such as phosphorus, arsenic, PH3 and AsH3, to implant the dopants in the polysilicon layer formed on the buried diffusion layer . Then, a silicon nitride layer is formed on the doped conductive layer for serving as a CMP (chemical mechanical polishing) stopping layer. The silicon nitride layer can be formed by a low pressure chemical vapor deposition method with reaction gases of SiH2Cl2 and NH3 at a temperature of about 700-800° C.

Referring to FIG. 2C, a plurality of trench regions is formed in the semiconductor substrate by a conventional photolithography and etching method. Then, a silicon dioxide layer is deposited over the silicon nitride layer to fill the trench regions. The silicon dioxide layer can be deposited by a low pressure chemical vapor deposition method with a reaction gas of TEOS (tetra-ethyl-ortho-silicate) at a temperature of about 650-850° C. and under a pressure of about 0.1-5 torr. Alternately, the silicon dioxide layer can be deposited by a plasma enhanced chemical vapor deposition method with a reaction gas of SiH4 at a temperature of 300-400° C. and under a pressure of about 1-10 torr. Planarizing the silicon dioxide layer until the silicon nitride layer by a chemical mechanical polishing method to form several shallow trench isolation regions in the semiconductor substrate , and making the buried diffusion layer to a plurality of bit lines. Then, the silicon nitride layer is removed with a wet etching method utilizing hot H3PO4 aqueous solution.

Referring to FIG. 2D, an interlayer dielectric layer is formed over the shallow trench isolation regions . The interlayer dielectric layer can be a silicon dioxide layer formed by the conventional chemical vapor deposition method, a BPSG (borophosphosilicate glass) layer formed by a plasma enhanced chemical vapor deposition method with reaction gases of TEOS (tetra-ethyl-ortho-silicate), O3, TEB (triethyl-borate) and TMPO (tri-methyl-phosphate) at a temperature of about 400˜500° C. and under a pressure of about 10 torr layer, a PSG (phosphosilicate glass) layer formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and PH3, a silicon nitride layer formed by a low pressure chemical vapor deposition method with reaction gases of SiH2Cl2 and NH3 at a temperature of about 700-800° C., and a silicon oxynitride layer formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and N2. Next, a photoresist layer (not shown) is formed on the interlayer dielectric layer and a photomask (not shown) with a mask ROM code pattern is placed on the photoresist layer to transfer the mask ROM code pattern to the photoresist layer. Thereafter, performing an anisotropic etching process using the photoresist layer as an etching mask to form openings in the interlayer dielectric layer unto the exposed regions of the doped conductive layer . Then, the photoresist layer is removed. Following, performing an ion implantation to form a diffusion region with a second conductivity opposite to the first conductivity in each of the exposed regions of the doped conductive layer , each diffusion region corresponding to a code area of the mask ROM. In the preferred embodiment, the diffusion region is a P+ diffusion region formed by an ion implantation with ion source, such as boron and BF2+. Thus, the P+ diffusion region and the N− doped conductive layer /the N+ buried diffusion layer constitute a PN diode cell, which can instead of a channel transistor used in the conventional mask ROM, serving as a memory cell. Until now, the coding process of the mask ROM is completed.

Referring to FIG. 2E, a contact plug is then formed in each opening and unto the exposed region of the doped conductive layer to constitute a structure of a contact plug/a PN diode. The structure of the contact plug/PN diode is used to serve as a memory cell instead of a channel transistor used in the conventional mask ROM. The contact plug can be a tungsten plug formed by a low pressure chemical vapor deposition method with reaction gases of WF6 and SiH4 at a temperature of about 300-550° C. and under a pressure of about 1-100 torr. A conductive layer is then formed on the interlayer dielectric layer and the contact plug to serve as word lines. The conductive layer is preferably a polysilicon layer formed by a low pressure chemical vapor deposition method with a reaction gas of SiH4 at a temperature of about 600-650° C.

In an alternative embodiment, the N− doped conductive layer can be omitted, and then forming the P+ diffusion region in the N+ buried diffusion layer to constitute the PN diode cell instead of a channel transistor to serve as a memory cell.

The preferred embodiments are only used to illustrate the present invention, not intended to limit the scope thereof. Many modifications of the preferred embodiments can be made without departing from the spirit of the present invention.

CLAIMS

1. A method for fabricating a mask read-only-memory with diode cells, comprising: providing a semiconductor substrate; forming a buried diffusion layer with a first conductivity in a top portion of said semiconductor substrate; forming a plurality of shallow trench isolation regions in said semiconductor substrate and then making said buried diffusion layer to a plurality of bit lines; forming an interlayer dielectric layer over said buried diffusion layer and said shallow trench isolation regions; forming a photoresist layer with a mask read-only-memory code pattern on said interlayer dielectric layer; performing an anisotropic etching process to form openings in said interlayer dielectric layer unto the exposed regions of said buried diffusion layer using said photoresist layer as an etching mask; removing said photoresist layer; performing ion implantation to form a diffusion region with a second conductivity opposite to said first conductivity in each of said exposed regions of said buried diffusion layer; forming a contact plug in each said opening unto said diffusion region; and forming a conductive layer on said interlayer dielectric layer for serving as word lines.

2. The method of claim 1, wherein said semiconductor substrate is selected from a group consisting of silicon substrate, germanium substrate and germanium arsenic substrate.

3. The method of claim 1, wherein said first conductivity is either of N type conductivity and P type conductivity.

4. The method of claim 1, wherein said interlayer dielectric layer comprises silicon dioxide formed by a chemical vapor deposition method.

5. The method of claim 1, wherein said interlayer dielectric layer comprises PSG (phosphosilicate glass) formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and PH3.

6. The method of claim 1, wherein said interlayer dielectric layer comprises BPSG (borophosphosilicate glass) formed by a plasma enhanced chemical vapor deposition method with reaction gases of TEOS (tetra-ethyl-ortho-silicate), O3, TEB (tri-ethyl-borate) and TMPO (tri-methyl-phosphate) at a temperature of about 400˜500° C. and under a pressure of about 10 torr.

7. The method of claim 1, wherein said interlayer dielectric layer comprises silicon nitride formed by a low pressure chemical vapor deposition method with reaction gases of SiH2Cl2 and NH3 at a temperature of about 700˜800° C.

8. The method of claim 1, wherein said interlayer dielectric layer comprises silicon oxynitride formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and N2.

9. The method of claim 1, wherein said contact plug comprises tungsten formed by a low pressure chemical vapor deposition method with reaction gases of WF6 and SiH4 at a temperature of about 300˜550° C. and under a pressure of about 1˜100 torr.

10. The method of claim 1, wherein said conductive layer comprises polysilicon formed by a low pressure chemical vapor deposition method with a reaction gas of SiH4 at a temperature of about 600˜650° C. and under a pressure of about 0.3˜0.6 torr.

11. A method for fabricating a mask read-only-memory with diode cells, comprising: providing a semiconductor substrate; forming a buried diffusion layer with a first conductivity in top portion of said semiconductor substrate for serving as bit lines; forming a doped conductive layer with said first conductivity on said buried diffusion layer, wherein the dopant concentration of said doped conductive layer is lighter than that of said buried diffusion region; forming a plurality of shallow trench isolation regions in said semiconductor substrate; forming an interlayer dielectric layer over said doped conductive layer and said shallow trench isolation regions; forming a photoresist layer with a mask read-only-memory code pattern on said interlayer dielectric layer; performing an anisotropic etching process to form openings in said interlayer dielectric layer unto the exposed regions of said doped conductive layer using said photoresist layer as an etching mask; removing said photoresist layer; performing ion implantation to form a diffusion region with a second conductivity opposite to said first conductivity in each of said exposed regions of said doped conductive layer; forming a contact plug in each of said openings unto said diffusion region; and forming a conductive layer on said interlayer dielectric layer for serving as word lines.

12. The method of claim 11, wherein said first conductivity is either of N type conductivity and P type conductivity.

13. The method of claim 11, wherein said doped conductive layer comprises doped polysilicon formed by an in-situ doped low pressure chemical vapor deposition method with a reaction gas of SiH4 and a dopant source of PH3 at a temperature of about 600˜650° C. and under a pressure of about 0.3˜0.6 torr.

14. The method of claim 11, wherein said interlayer dielectric layer comprises silicon dioxide formed by a chemical vapor deposition method.

15. The method of claim 11, wherein said interlayer dielectric layer comprises PSG (phosphosilicate glass) formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and PH3.

16. The method of claim 11, wherein said interlayer dielectric layer comprises BPSG (borophosphosilicate glass) formed by a plasma enhanced chemical vapor deposition method with reaction gases of TEOS (tetra-ethyl-ortho-silicate), O3, TEB (tri-ethyl-borate) and TMPO (tri-methyl-phosphate) at a temperature of about 400˜500° C. and under a pressure of about 10 torr.

17. The method of claim 11, wherein said interlayer dielectric layer comprises silicon nitride formed by a low pressure chemical vapor deposition method with reaction gases of SiH2Cl2 and NH3 at a temperature of about 700˜800° C.

18. The method of claim 11, wherein said interlayer dielectric layer comprises silicon oxynitride formed by a plasma enhanced chemical vapor deposition method with reaction gases of SiH4, N2O and N2.

19. The method of claim 11, wherein said contact plug comprises tungsten formed by a low pressure chemical vapor deposition method with reaction gases of WF6 and SiH4 at a temperature of about 300˜550° C. a pressure of about 1˜100 torr.

20. The method of claim 11, wherein said conductive layer comprises polysilicon formed by a low pressure chemical vapor deposition method with a reaction gas of SiH4 at a temperature of about 600-650° C. a pressure of about 0.3-0.6 torr.

COPYRIGHT

User acknowledges that Fairview Research and its third party providers retain all right, title and interest in and to this xml under applicable copyright laws. User acquires no ownership rights to this xml including but not limited to its format. User hereby accepts the terms and conditions of the License Agreement.