Method for fabricating MIM capacitor

ABSTRACT

Disclosed is a method for forming a MIM capacitor, the method comprising steps of: providing a semiconductor substrate formed with a base layer including a metallic pattern; depositing a first metallic layer to be used for a lower electrode on the base layer; depositing a first middle layer on the first metallic layer in order to improve the surface roughness of the first metallic layer and prevent oxidization thereof; depositing a dielectric layer with a high dielectric constant on the first middle layer; depositing a second middle layer on the dielectric layer in order to increase band gap energy; depositing a second metallic layer used for the upper electrode on the second middle layer; and completing the formation of the lower electrode by patterning the first metallic layer.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS

Hereinafter, a preferred embodiment of the present invention will be described with reference to the accompanying drawings. In the following description and drawings, the same reference numerals are used to designate the same or similar components, and so repetition of the description on the same or similar components will be omitted.

FIGS. 2A to D are explanatory views in cross section illustrating a method for forming an MIM capacitor according to an embodiment of the present invention.

Referring to FIG. 2A, a base layer , which includes a copper pattern or an aluminum pattern (not shown) formed by a dual damascene process, is formed on a semiconductor substrate . Afterward, a first metallic layer, i.e., a barrier layer of TiN, TaN, Ti or Ta, is deposited on the base layer , and then a first nitride layer is deposited on the barrier layer with a thickness within a range of 10 to 200 Å by a PECVD (plasma enhanced chemical vapor deposition) process performed at a temperature range of 300 to 500 degrees Celsius.

Here, since the barrier metallic layer has a poor surface roughness with respect to the fact that the metallic barrier layer of TiN, TaN, Ti or Ta has a columnar structure the first nitride layer is formed in order to mitigate surface roughness. Tn this respect, a silicon oxide (SiO2) layer or an aluminum oxide (Al2O3) layer can be used instead of the nitride layer.

Referring to FIG. 2B, a Ta2O5 layer having a high dielectric constant is deposited as a dielectric layer on the first nitride layer . The Ta2O5 layer has a thickness within a range of about 30 Å to about 1000 Å. Then, in order to ensure the material property of the Ta2O5 layer , post treatment, such as an O2-plasma treatment or an O3 -annealing, is performed. Here, an O2-plasma treatment is carried out with a power of between 200 and 300 watts for a time of between 10 and 300 seconds using O, N2, Ar gas. Also, the O3-annelaing is carried out at a temperature of between 200 and 500 degrees Celsius for a time of between 1 and 300 minutes.

In such a post treatment, the surface of the metallic barrier layer of the present invention will not be oxidized because the first nitride layer is formed on the metallic barrier layer , while in contrast, the surface of the metallic barrier layer of the prior art is oxidized.

As a material with high dielectric constant, a HfO2, HfON, BST, ZrO2, CeO2, TiO2, Y2O3 or ternary metallic oxide layer can be used instead of the Ta2O5 layer .

Referring to FIG. 2C, on the Ta2O5 layer is deposited a second nitride layer with a thickness of between 10 and 200 Å by the PECVD process performed at a temperature of between 300 and 500 degrees Celsius.

Here, the second nitride layer is formed so as to provide symmetry. In particular, the band gap energy of the second nitride layer is greater than that of the Ta2O5 layer , so that the movement of electrons and holes is interrupted. As a result, the second nitride layer improves the ability of the capacitor to prevent leakage current.

Also, if the second nitride layer is deposited on the Ta2O5 layer , the post treatment followed by the deposition of the Ta2O5 layer may be omitted, because the reduction in leakage current due to the band gap is ensured.

Referring to FIG. 2D, a second metallic layer, which is used for the upper electrode and is made from TiN, TaN, Ti or Ta, is deposited on the second nitride layer by a CVD or a sputtering process. Thereafter, an upper electrode is formed by patterning the second metallic layer, the second nitride layer, the Ta2O5 layer and the first nitride layer. Also, the lower electrode is formed by patterning the metallic barrier layer. As a result, the MIM capacitor of the present invention is formed.

Subsequently, though not shown in the drawings, metallic wires are formed in contact with the lower electrode and the upper electrode by a wiring process, and thus the production of the MIM capacitor is completed.

As described above, the process of producing the MIM capacitor of the present invention can mitigate surface roughness by interposing a nitride layer between the lower electrode and the upper electrode. Further, since oxidization on the surface of the lower electrode is prevented in the post treatment of the dielectric layer, it is possible to improve the ability of the capacitor to prevent leakage current as well as improve the polarity. These improvement of leakage current also improve the RF and analog characterizations, which are VCC, TCC and so on.

Also, because the MIM capacitor of the present invention has nitride layers interposed between the lower electrode and the dielectric layer as well as between the dielectric layer and the upper electrode, respectively, it is possible to improve the ability of the capacitor to prevent leakage current due to a band gap energy effect as shown in FIG. . In other words, while the band gap energy of the Ta2O5 layer is 4.5 eV, that of the nitride layer deposited by the PECVD process is 5.1 eV. Accordingly, obstruction to the passage of the electrons and the holes is relatively high, so that it is possible to gain an effect of reducing the leakage current.

Also, since the nitride layers are respectively interposed between the lower electrode and the dielectric layer as well as between the dielectric layer and the upper layer, the post treatment for the dielectric layer, such as the Ta2O5 layer may be omitted.

FIG. 4 is a graph illustrating leakage current versus voltage characteristics. It shows a comparison of a first case in which a positive (+) bias is applied to the upper electrode to a second case in which a negative (−) bias is applied to the upper electrode.

When only the dielectric layer is present without an interposed nitride layer, as indicated with curve A, there exists a great difference. When the nitride layer is interposed only between the lower electrode and the dielectric layer, as indicated with curve B, the difference is reduced. When the nitride layers are interposed between the lower electrode and the dielectric layer as well as between the dielectric layer and the upper electrode, respectively, as indicated with curve C, the difference is reduced.

Accordingly, the MIM capacitor according to the present invention improves the ability of the capacitor to prevent leakage current as well as improving the polarity, by interposing the nitride layers above and below the dielectric layer by the PECVD process.

As described before, the present invention improves the polarity and the ability to prevent leakage current by interposing a nitride layer between the lower electrode and the dielectric layer as well as between the dielectric layer and the upper electrode by a PECVD process, thus improving the performance of the MIM capacitor as well as the reliability thereof.

Although a preferred embodiment of the present invention has been described for illustrative purposes, those skilled in the art will appreciate that various modifications, additions and substitutions are possible, without departing from the scope and spirit of the invention as disclosed in the accompanying claims.

BRIEF DESCRIPTION OF THE DRAWINGS

The above and other objects, features and advantages of the present invention will be more apparent from the following detailed description taken in conjunction with the accompanying drawings, in which:

FIG. 1 is a cross-sectional view of an MIM capacitor according to a prior art.

FIGS. 2A to D are explanatory views in cross-section illustrating a method for forming an MIM capacitor according to an embodiment of the present invention.

FIG. 3 is an explanatory view illustrating an energy band gap of the MIM capacitor according to the present invention.

FIG. 4 is a graph illustrating leakage current (I) to voltage (V) characteristic in an MIM capacitor.

CLAIMS

1. A method for forming an MIM capacitor on a semiconductor substrate having a base layer, the method comprising steps of: forming a first metallic layer on the base layer; forming a first middle layer of an aluminum oxide layer on the first metallic layer in order to improve the surface roughness of the first metallic layer and prevent oxidization thereof; forming a second middle layer from one of HfO2, HfON, BST, ZrO2, CeO2, TiO2, and Y2O3 on the first middle layer; forming a third middle layer of an aluminum oxide layer on the second middle layer in order to increase band gap energy; forming a second metallic layer on the third middle layer.

2. A method for fabricating an MIM capacitor as claimed in claim 1, wherein each of the first end second metallic layers is made from one of, TI and Ta.

3. A method for fabricating an MIM capacitor as claimed in claim 1, wherein the second and third layers are deposited with a thickness of between 10 and 200 Å by a PECVD process performed at a temperature of between 300 and 500 degrees Celsius.

4. A method for fabricating an MIM capacitor as claimed in claim 1 wherein the second middle layer is formed by utilizing an O2-plasma treatment process or an O3-annealing process.

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