Skew calibration means and a method of skew calibration

ABSTRACT

A high speed communication apparatus with means for reducing timing uncertainty providing a high accuracy of transferring and receiving signals by intelligent skew calibration of the apparatus. The system for reducing timing uncertainty of a communication apparatus comprises a plurality of driving registers for transmitting signals; a plurality of receiving registers for receiving signals; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the registers; and a plurality of phase shift means comprising at least one set of phase shift means associated with each said plurality of registers, for the relative alignment of the register's timing within each plurality. The apparatus preferably further comprises a storage means for recording and storing information on skew in a communication media, for at least one data pattern transmitted through the transmission line and a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above skew.

INFORMATION

DETAILED DESCRIPTION OF THE INVENTION

This is a Continuation-in-Part of application Ser. No. 09/342,227 (Confirmation No. Not Assigned) filed Jun. 29, 1999, which is a continuation-in-part of PCT application PCT/RU98/00204 filed Jun. 29, 1998 and PCT/RU99/00193 filed Jun. 10, 1999.

This application also claims priority from U.S. Provisional Application No. 60/244,179 filed on Oct. 31, 2000 and from Provisional Application No. 60/310,299 filed Aug. 6, 2001.

This application is based upon earlier filed applications PCT/RU98/00204, filed Jun. 29, 1998, PCT/RU99/00194, filed Jun. 10, 1999, and GB 0111181.4 filed on Apr. 2, 2001, the disclosures of which applications are herein incorporated by reference.

BRIEF DESCRIPTION OF THE DRAWINGS

For a better understanding of the present invention and the advantages thereof and to show how the same may be carried into effect, reference will now be made, by way of example, without loss of generality, to the following description now taken in conjunction with the accompanying drawings in which:

FIG. 1 is a fragmentary circuit diagram of the skew calibration means in accordance with one of the embodiments of the present invention;

FIG. 2illustrates a method of introducing a common node according to a prior art method;

FIG. 2illustrates the transmission line for introducing a common time base according to the invention;

FIG. 2illustrates the transmission line with a series of switches for introducing a common time base according to the invention;

FIG. 3 is a flow chart diagram of the operation of a skew calibration means in accordance with the present invention;

FIG. 4shows a graph of the step of calibration of registers performed by incrementing the delay corresponding to the register from zero to maximal value;

FIG. 4shows a calibration graph for a programmable delay and illustrates the first step of calibration according to the present invention;

FIG. 5 is a timing diagram illustrating the skew calibration method in accordance with the present invention;

FIG. 6 shows a schematic block diagram of the test system in accordance with the present invention.

FIG. 7 shows a general block diagram of a timing uncertainty reduction system according to the second embodiment of the present invention.

FIG. 8 shows the phase noise characteristic, both ideal and actual for a common component, a SSTL16857 register with input noise, with relative time in pico seconds in the X axis and probability density of receiving the wrong bit with a scaling factor in the Y axis.

FIG. 9 shows the Bit Error Rate (BER) as a function of the number of standard deviations of a normal distribution, from which a temporal operating window is chosen.

FIG. 10 shows an example of the probability of a signal being latched as a 1 by a register as a function of a timing offset.

FIG. 11 shows an example of a variation in the probability of a signal being latched as a 1 as a function of the data, namely the frequency at which the data changes.

FIG. 12 shows a simple sample—hold circuit.

FIG. 13 shows a simplified delay calibration configuration.

FIG. 14 is a timing diagram.

The invention will now be described, without loss of generality, with the aid of example embodiments.

DETAILED DESCRIPTION OF THE INVENTION

In FIG. 1 a fragmentary block scheme of a tester header with a built-in skew calibration means in accordance with one of the embodiments of the present invention is shown. The remaining circuitry partially shown in FIG. 6 is conventional circuitry containing different elements, such as formatters, master clocks, programmable delays, switches, etc, which are utilised to generate the test signals. The calibration means of the present invention is adapted for providing calibration of test data between the actual transmitting and receiving registers and the DUT. Typically used registers include conventional flip-flops and latches.

Illustrated in FIG. 1 are a plurality of input registers - for transmitting test signals to the device under test (DUT), including data, address and control signals transmitted from the registers, and a plurality of output registers - for receiving response signals from the DUT. The clock signals are transmitted to the DUT from the main clock driver via, sequentially, a programmable delay and a logic translator means .

The outputs of the input registers , are connected to the DUT and to the inputs of the output registers -. The clocks of the input registers , are connected via logic translator means , and delays , , respectively, to the output of the secondary clock driver for maintaining data setup time for the input registers and DUT. To achieve this, the input of the secondary clock driver is connected via programmable delay to the main clock driver .

The clocks of the output registers ,, are connected via logic translator means , and and delays , and to the output of the secondary clock driver . The input of the secondary clock driver is connected via programmable delay to the main clock driver for alignment of the fault strobe to the DUT clock. One more set of registers - is adapted to allow the signal entering the input registers to be independent from the path length from the baseboard; the inputs of the registers - are connected to the baseboard, while their outputs are connected to the inputs of the input registers -. The clocks of the registers , are connected via logic translator means and , respectively, to the main clock driver . It should also be noted that the number of registers is not limited and may be, for example, one hundred or more. A main clock driver is provided for generating timing signals for the tester. Preferably, the main clock driver generates clock signals at different frequencies.

To perform the calibration of the tester, programmable delays , , are provided to compensate for the differences in signal paths from the DUT and delays , are provided to compensate for the differences in signal paths to the DUT. Generally, the set of phase shift means (e.g., programmable delays) may comprise, for example, one or more shift means for relative alignment of the registers's timing within each plurality, i.e. the number of delays may be less or greater than the number of registers within each plurality.

Preferably, at least one calibration shift means is used for delaying the timing of each separate register within the plurality, as shown in FIG. 1; i.e. delays , are used for calibrating the timing of the input registers ,, respectively, while delays ,, are used for calibrating the timing of the output registers ,, respectively.

Another set of phase shift means, in this case, including delays , and , is reserved for shifting secondary clocks in relation to main clock to provide individual fan-out for the registers. The second set of phase shift means is also used for relative alignment of the register's timing between the said pluralities. Preferably, at least one delay from the second set of delays is associated with each of the plurality of registers. As seen in FIG. 1, both the plurality of input registers and the plurality of output registers are connected to the main clock means via the said second set of phase shift means.

Any suitable means may be used for phase shifting, e.g. as already mentioned above, conventional programmable delays. The delays may be implemented, for example, using a SY100E195 manufactured by Synergy Semiconductor Corp. (U.S.A.), or by Analogue Devices, or by Edge Semiconductor Devices.

In order to maintain the timing skew within the predetermined accuracy during the testing operation and in case a new type of memory device is to be tested, it is necessary to be able to calibrate the test system periodically to determine whether any changes have occurred as a result of temperature variations, aging, or any other factors. To perform the calibration operation, a reference clock driver for supplying the reference clock signal for the registers is incorporated in the circuit and connected to the registers through reference clock switches and During normal operation mode, switches are open and the reference clock is disconnected from the data lines.

It should also be noted that the common time base, i.e. the main clock, is introduced into the calibration circuit in accordance with the present invention by means of a “distributed common node”. In a typical skew calibration circuit, e.g. as described in U.S. Pat. No. 4,827,437, a common node is introduced by means of multiple cables disposed between the node and each test terminal, each of the cables identical in length and internal impedance (see FIG. 2). According to the present invention, a common transmission line of known wave characteristics is used to create the common time base which is available at different points in the circuit, as shown in FIG. 2Thus, each point connected to the transmission line is provided with a common time base which may easily be calculated from the signal propagation rate in this transmission line. As a result, there is no necessity to use cables of equal length to provide a common time base. The transmission line may be provided with a series of switches to commutate registers as desired, as shown, for example, in FIG. 3Different switch patterns can be created as it is evident for a specialist in the art.

Referring to FIG. 1, the reference clock signal is distributed from the reference clock driver to the registers ,, via a common transmission line. Each output register ,, is series-connected to the said transmission line, permitting a transmission line of a minimal length to be used and thus minimising the signal fluctuations along the line.

If necessary, as shown in FIG. 1, a number of logic translator means - of a PECL-to-TTL type, e.g. SY100ELT23 manufactured by Synergy Semiconductor Corp. (U.S.A.), may be provided for translating PECL signals used in the clock circuit into TTL signals used in the DUT circuit. However, in particular applications these translators may not be needed and may be omitted.

The operation of the skew calibration means will now be described in more detail.

The calibration procedure is performed in four operations comprising:

(1) calibrating each programmable delay to determine its actual delay characteristics;

(2) calibrating a plurality of output registers in relation to the reference clock edge;

(3) calibrating the propagation delay of the input registers using the calibrated output registers;

(4) providing relative alignment of the measured delays

to the main clock edge.

The first three of these four calibration operations are performed using a special calibration technique proposed in the present invention. The technique comprises varying the programmable delay using a system sequencer (not shown) to cover the whole delay range and determining for each bit of the register the probability that it will be in one of the possible states, i.e. the “0” or “1” state. The calibration is performed by incrementing the corresponding delay from zero to maximal value; the result Si of i-determination for a given bit of a given register is calculated R times at given conditions, each determination being repeated until a statistically sufficient number R of meanings is obtained. The flow chart of this calibration operation is shown in FIG. 3, where ΣSi/R is an averaged result of the above determination.

On the basis of the data obtained, a graph is plotted showing the point where the above probability is equal to 50%. The graph of this calibration operation is illustrated in FIG. ().

A computer program can be easily created in any suitable language, e.g. C, C++, Assembler, etc, to implement the above calibration operation on the basis of a flow chart represented in FIG. .

I. Calibration of Programmable Delays

The first operation of the calibration procedure can be omitted in certain cases and it is preferably performed before the calibration of the registers. The operation comprises a preliminary calibration of the programmable delays that are used for calibration of registers, and ensures a high precision calibration.

Programmable delays are characterised by the linear dependence of the delay value on a code that is sent to the delay (a typical graph of this dependence for delays A and B is shown in FIG. ()). As shown in the figure, the slope of this linear graph varies from one delay to another within the same batch. It is also known that the calibration frequency influences the moment at which the transition occurs from one of the two possible states to the other. Inaccuracy caused by this influence is accounted for at this step. To define the delay characteristics accurately, each programmable delay is calibrated in situ after being installed in a calibration circuit but before the calibration of the registers. The delays are calibrated by varying the calibration frequency while keeping other variables constant, that making it possible to determine the threshold of the variable delay by fixing the difference in time of the two transition moments.

It should also be noted that in the course of this procedure a calibration graph is obtained with x, y coordinates, where ‘x’ is the clock period and ‘y’ the discrete delay unit (d, delay counts). To define the linear dependence in terms of time units (Td) along the y coordinate, the value of this discrete unit is determined in time units by the standard method of linear regression. Thus, each variable delay is assigned a transfer function Ftr showing the dependence of the delay value on the code that is sent to the variable delay.

II. Calibration of Output Registers

The second operation is the calibration of each or at least some of the output registers in relation to the reference clock edge (although in this case, registers , and are shown in FIG. 1, it shall be understood that in practice the number of registers may be one hundred or more.) During the calibration operation, one of the switches is closed, depending on which bit of the register being calibrated is to be measured. For example, to calibrate register , the middle switch shall be closed and input registers are tri-stated. Then the corresponding programmable delay is varied to cover the whole delay range in accordance with the calibration procedure described above. In this case, the procedure is performed at the same frequency for different bits of the register.

This operation may be omitted in the case of new generation high-precision registers, or where registers specially manufactured for this purpose are provided, or where pre-calibrated registers are used. Conventional registers may also be used without adjustment, but there will be a certain decrease in the overall accuracy of the system.

A timing diagram of this calibration operation is illustrated in FIG. . As shown in FIG. 5, a certain difference in time is observed between the moment when the register actually latches input data and the reference clock edge. At the end of the calibration procedure, corresponding delays, i.e. Td for a given bit in a given register, are introduced into the input and output channels to compensate for these time differences, Td being defined by the following formula:

dlar,

where Td—actual value of signal delay;

Tla—an exact time of data latching in the register;

Tr—time required for the reference clock signal to reach a given bit of a given register via a transmission line. This time may be calculated from the PCB (printed circuit board) layout and/or checked and corrected by oscilloscope measurements.

However, uncertainty in determining the length of the delay to be nulled limits the accuracy of the calibration operation and, therefore, this uncertainty shall be minimised. Parameter Tla, representing the exact time of data latching in the register, is defined by an average of the setup and hold times for an actual register under given power supply and temperature conditions. However, this parameter may differ from the parameters indicated in datasheets, as these usually give the worst case values over temperature and power supply. Determining the actual time when the register latches the input data and the actual delay between this moment and the reference clock edge enables the accuracy of the test system operation to be increased. The determination is performed either for the falling edge, or for the rising edge of the reference clock, or it may be performed twice, once for the falling edge, and again for the rising edge to assure the accuracy. The accuracy of determining Td (time of delay) and therefore, Tla, as Tr (time of reference clock edge) is a function of two values: register clock jitter and latch time uncertainty itself. Because of the difficulty of achieving an accurate calculation of the jitter and latch time window of uncertainty, the sum of these two values is determined experimentally. It has been found that the delay Td may be determined with an accuracy of 250 ps for both rising and falling edges of data at the input of typical TTL registers. Greater accuracy is available from some CMO Gallium Arsenide and ECL registers.

The accuracy of calibration of the output registers can now be determined on the basis of the experimental data. It is limited by the uncertainty of the actual time when the register latches data and is calculated as follows:

sk(out)sk(o)unc,

where ΔTsk(o) is the output skew of the reference clock driver which is equal to about 0.3 ns for a typical clock driver, e.g. SY100E111 manufactured by Synergy Semiconductor Corp. (U.S.A.). This skew can be reduced during the manufacturing process, but for the purposes of the present description it may be assumed that standard devices are used without adjustment. Alternatively, a single line having predetermined signal propagation parameters may be used. In this case, ΔTsk(o) may be determined from the PCB (printed circuit board) layout and will be less than 0.3 ns;

ΔTunc is the uncertainty of determining the difference in time between the moment when the register actually latches input data and the reference clock edge, and is determined to be in this case ±0.25 ns. This could also be measured as noted above. Though this accuracy may be assumed sufficient for the example embodiment of the present invention, in general, the proposed calibration means provides a scalable system capable of being adjusted to whatever increased accuracy may be desired when using registers with a higher inherent accuracy.

As for the main clock driver jitter, it is negligible, since the main clock driver is commonly implemented in a positive emitter coupled logic (PECL). Commercial Hybrid oscillators are able to achieve a 3 ps RMS (Root Mean Square) jitter. It shall also be noted that the output skew of the main clock driver is in any case compensated for in the course of the proposed calibration operation due to the averaging of data. Thus, typically,

sk(out)=0.30+0.25=0.55 ns.

Thus, the output registers are calibrated with an accuracy of at least 0.55 ns, preferably less than 0.55 ns.

III. Calibration of Input Registers

The third skew calibration operation is the calibration of the propagation delay of each of the plurality of input registers ,. To perform the third operation of the calibration, the reference clock driver is disconnected from the calibration means by opening all the switches . Then, input registers , are forced by the timing generator to produce either low-to-high or high-to-low transition on their outputs. The measurements may be performed for each individual bit of data transmitted from the output register, for which the best match with the latch time of the input registers - is found by varying the corresponding delays or . A similar procedure is performed to find the best match the data transmitted from output register with the latch time of clock driver . As a result, Td(DUTclk) is obtained. Although the delay shifts clock for the whole register, individual bits may be monitored and individual propagation delays may be obtained for each output bit of data from the input register. The accuracy of this measurement is limited by the accuracy with which delays have been determined at the previous step and may be calculated as follows:

sk(in)sk(out)unc,

where ΔTsk(out) is the accuracy of calibration of the output registers and is about 0.55 ns, as calculated above; ΔTunc is the uncertainty of determining the difference in time between the moment when the register actually latches input data and the reference clock edge, in this case, ±0.25 ns.

sk(in)=0.55+0.25=0.80 ns.

Thus, the input registers can be calibrated with an accuracy of at least 0.80 ns, preferably less than 0.80 ns.

IV. Relative Alignment of the Measured Delay

The final calibration operation is the relative alignment of the measured delay to the main clock.

After completion of the calibration procedure, the DUT clock is chosen as the reference clock to represent the calibration results. The corresponding delay compensation values, Tcomp, are input by the central control means into the programmable delays. This compensates for the major part of the skew.

However, there is still some remainder internal register skew, i.e. skew between pins of the same register (the number of pins may be, e.g. from 4 to 18), that cannot be compensated for in the course of the calibration procedure. For estimation of this skew by the user and for the purposes of convenience, this skew is measured to report it to the user together with the calculated compensation values. Skew of the each signal is calculated in relation to the DUT clock which is thereafter assumed to be zero. The following procedure is performed to determine the compensation values of the delays, wherein

k is a bit number within a given plurality of registers, all bits within this plurality being numerated serially from the first bit of the first register to the last bit of the last register;

n is an input register's number within the given plurality of input registers, the total number of input registers being N;

m is an output register number within the plurality of output registers, the total number of output registers being N+1, which exceeds by one the number of input registers due to the presence of clock driver which output is connected to the input of one of the output registers.

Step 1

The following data are input to determine the compensation values of the delay:

calibration graphs in digital form, obtained at operation II for each mth output register and for each kth bit of the output register;

individual reference clock delay values Trk measured for each kth bit of the output register;

Step 2

Determine Tdk for each bit k as Tdk=dk×Ftr, where Ftr is a transfer function which is determined at operation I and dk is defined by 50% level for each kth bit for the mth output register;

determine Tlak=Tdk−Trk for each kth bit of the output register;

Step 3

determine an average meaning of Tlak of all bits for mth output register as

where km is the first bit number of the output register m;

determine minm;

calculate compensation delays as

compm(out)=m−min;

Step 4 (Determining Propagation Time for Each Input Register)

for each nth input register take Tdk(in) determined in operation III;

for each nth input register take Tlak(out) determined in Step 2 for each mth output register which input is connected to the output of the nth input register;

calculate Tcok(in)=Tdk(in)−Tlak(out); where Tco is “clock-to-output”, i.e. propagation time;

calculate an average meaning of Tcok of all bits for mth output register as

determine minn;

calculate a set of compensation delays for each input register as Tcompn(in)=−min;

Step 5

take Td(DUTclk)k determined at operation III for DUT clock driver when the reference clock is switched off and the DUT clock is connected to the output registers;

take Tla(DUTclk)k for the output register which input is connected to the output of the DUT clock driver;

calculate Tcok(DUTclk)=Tdk(DUTclk)−Tlak(DUTclk); where Tco is “clock-to-output”, i.e. propagation time;

calculate an average meaning of Tco(DUTclk) for each kth bit of the clock driver as:

where kDUT is the number of the first bit of the output register to which DUT clock is connected; L is the number of DUT clock;

calculate compensation delay for each DUT clock driver as Tcomp(DUTclk)=Tco(DUTclk)−minn.

A computer program can be easily created in any suitable language, e.g. C, C++, Assembler, etc, to implement the above sequence of steps on the basis of the above description.

The following errors may cause inaccuracy in the register's calibration.

Different registers may differ in their threshold level, causing uncertainty of their electric parameters. Using the method of calibration discussed above, it is possible to obviate or at least alleviate this problem.

Registers typically have threshold voltage of about 1.5-1.6V, while the threshold for SDRAM's is about 1.4V. This may also cause errors in determining the transition between “0” and “1” states. In this case, it is possible to calculate the error in determining the time difference between the moment when the register actually latches data and the reference clock edge, which is represented by the formula

trh

where

Δttrh—the addition to the time difference between the moment when a register actually latches data and a reference clock edge, caused by threshold voltage differences;

actual−standard;

r—a signal's slew rate.

For the register's threshold voltages of about 1.5-1.6V, and SDRAM's threshold voltage of about 1.4V, as mentioned above, ΔU=1.5V−1.4V=0.1V; a signal slew rate r is about 2V/ns; thus, the uncertainty Δttrh is about 0.05 ns. In case U actual is 1.6V, the uncertainty will be even greater, i.e. about 0.1 ns, which constitutes a substantial part of the calibration accuracy. This is the systematic error that can be corrected as follows:

compncon>−min

Another possible source of errors that must be taken into account when calibrating the registers at this step is the bushold circuit of the register that has a remnant memory of the preceding state of the register. Due to the existence of this remnant memory, the threshold values for the up-to-down and down-to-up transitions are different. This phenomenon causes a hysteresis loop in FIG. 3By measuring the loop width Δthys it is possible to estimate the register's lowermost threshold uncertainty as follows:

unc.eff.unc.hys/2.

In FIG. 6 an example embodiment of the memory test system in accordance with the proposed invention is presented. The system shown is intended for testing a semiconductor memory (DUT), for example SDRAM DIMM module. The system contains a timing means for generating delay timing signals; a plurality of drivers wherein at least one driver is a register, with a set of phase shift means; a plurality of receivers, wherein at least one receiver is a register, with a set of phase shift means; a fault logic means ; and a central control unit connected to a computer interface .

The timing means provides an appropriate sequence of addresses, data and control signals for accessing memory elements within the DUT in accordance with the first step of the method of testing semiconductor devices proposed in the present invention. These data are fed to a set of input registers whose function in the memory test system in accordance with one of the embodiments of the present invention is to maintain a predetermined standard level of logic signals including write data, addresses and control signals applied to the DUT . A set of pin drivers (not shown) may be used for conditioning logic levels to the needs of a specific DUT. A set of phase shift means (e.g., programmable delay means) is used for calibration purposes to match the input timing of multiple test signal patterns. The read data obtained from the DUT are received by a set of receivers (e.g., output registers) and compared with the predetermined levels of “0” and “1” in a fault logic means to detect failures in the memory elements according to the next steps of the method of testing.

An analog comparator (not shown) may also be used before the output registers to compare the predetermined levels. From the output registers , the data in digital form are entered into a fault logic means which compares real data with expected data coming from the timing means . Another set of phase shift means (e.g., programmable delay means) for delaying received data to compensate the round trip delay, is used before the set of receivers (e.g., output registers). The fault data from the fault logic means are sent to the central control unit and further to a computer interface of a controlling computer (not shown) for processing test results according to the third step of the method of testing. The controlling computer preferably holds the accumulated data in an encoded format. The fault data may be represented also in a bitmap format for viewing the faults.

Instead of using conventional pin electronics for per-pin addressing of the DUT, the system shown in FIG. 6 uses two sets of registers, one for inputting data and another for receiving test data from the DUT. To achieve the strict accuracy required for testing high-speed semiconductor devices, conventional methods involve calibration of timings of each per-pin structure. The present invention avoids using time-consuming per-pin calibration by using a calibration means for calibrating registers thus enabling a fast per-register mode of calibration. In accordance with the present invention, the calibration operation may be performed both when the DUT is disconnected from the system, or, preferably, with the DUT connected to the test system. As the electrical characteristics of DUT itself may influence greatly the operation of the registers, it is highly important to be able to calibrate the test system by using the actual DUT to be tested, not by customary emulation of DUT characteristics.

Moreover, after the calibration operation is carried out in relation to the test system, the DUT registers may be calibrated as well. In this case the order in which the DUT registers are calibrated is not critical.

The present invention can also perform an analysis of DUT features, or any other integrated circuit device testing. For example, different DUT properties, e.g. electrical characteristics, may be examined in the course of the proposed test procedure. Thus, to determine the DUT pin capacitance, the calibration system is first calibrated as above. Then, a series of capacitors having predetermined capacitance values is tested using the same calibration system and measuring system parameters. The results obtained are plotted in the form of a calibration curve to determine the dependence of the system parameter P on the device capacitance, P=f(Capacitance). The next step is to measure the same system parameter using a DUT to be tested in place of a capacitor. The desired DUT pin capacitance can be easily calculated from the calibration curve. As an alternative, a register in a memory test system or any other receiver coupled with a transmitter may be used.

Another example embodiment of the invention is particularly applicable to interfaces between integrated circuits and for high speed communications.

In FIG. 7, this embodiment is illustrated in its most general form.

A timing uncertainty reduction system according to the invention comprises an input register (which may equally comprise a plurality of registers), an output register (which may comprise a plurality of registers as well), a main clock , a reference signal associated with the main clock, for calibrating the registers, and a plurality of phase shift means, such as vernier devices for the relative alignment of registers' timing. The present embodiment of the invention is capable of compensating not only for the skew between signals on the output of the register (or, registers) , but also the skew caused by intersymbol interference, i.e. depending on the history of previously transmitted bits, and the skew caused by crosstalk between adjacent lines, using the same calibration method.

As shown in the figure, data is presented as a plurality of signal wires into a multiplexer , which is controlled by a master state machine such that it can select either the incoming data or calibration data .

The data selected in the MUX then passes through a pipeline of registers , and : only three pipe stages are shown but the number of pipe stages is preferably twice the number of symbols that are stored in transmission medium due to the propagation delay of the medium.

The pipeline finishes in a register which may or may not be part of the monitoring pipe, depending on the access time of the content addressable memories and (which may be implemented in Look Up Tables, or LUTs), plus the summation time , plus the write time to the verniers . Variable delays, such as verniers , may be incorporated into the data signal line, or into the clock line which clocks output data.

The pipeline feeds two sets , of Look Up Tables (LUTs), wherein one set allocates one LUT per signal wire, and the second set of LUTs wherein one LUT is allocated across adjacent signal wires or in the ultimate case, all signal wires. Accordingly, shift registers or parallel registers may be used to address the lookup tables.

The purpose of the first LUT is to use the data being sent to look up a correction value which is written into the LUT by the State Machine during or at the end of the calibration process to correct for skew caused by intersymbol interference.

The purpose of the second LUT is to use the data being sent to look up a correction value which is written into the LUT by the State Machine during or at the end of the calibration process to correct for skew caused by cross-talk and other effects in neighbouring signals.

The register at the end of the pipe and the receiving register should have low variations with temperature and other factors. The output of the transmitter register feeds into a bank of vernier delays , with the delay setting determined by the composition, for example, such as by the summation of the delay values in each of the LUTs that relate to that signal wire. In the figure only one summation unit is shown for reasons of clarity but each pair of LUTs and has a summation unit which feeds in a similar fashion to the appropriate vernier.

The verniers delay the signals being sent into the transmission line via buffers or drivers .

The verniers may be located at the far end as an alternative to or in addition to locating them at the transmitting end.

At the receiving end, the signal may be buffered by buffers , then pass through a switch and an EXOR gate which is used in the calibration process, into a receiving register . The purpose of the gate shown in idealised form in FIG. 7 is to place a time window on the data during calibration so that the effect of timing anomalies can be determined for each bit of a known data stream. The gates may be NOR gates or NAND gates or any other gating function that has the functional equivalence of a switch. The EXOR gates are needed in some implementations to invert the incoming data stream. Any other form of selective inversion may be used.

The data, after being latched by the receiving register , enters the system for use as a data channel , but may also be switched to a counter . An analogue alternative to the counter is a low pass filter and integrator.

The output of the counter is fed into a receiving State Machine . This same state machine controls the gating of data during a calibration process, such as by the use of a counter and comparator which is operated synchronously to gate in a specific data bit from a serial stream to the register and gate out data bits that are not of interest in a particular calibration step.

The second or Slave State Machine can communicate with the Master State Machine either using the communication channel in a transceiver mode or using additional wires . The speed of this communication between state machines is very low in comparison with the data rate of the channel and latency is not of significant interest so any type of communication channel can be used for this connection between the state machines. The master State Machine controls the system clock using a source of a periodic signal of a variable precision frequency , for example a frequency synthesiser comprising VCO, divider chains, stable frequency reference and phase comparator such as a Synergy SY89S429. Alternatively or in conjunction with the variable frequency source, the master State Machine controls the data pattern during calibration .

The two state machines form a feedback loop.

The state machines together form a central control unit and run a calibration method according to the invention as has already been described in detail above whereby different frequencies or data patterns are used to determine the time between two edge events in terms of the actual delay of logic elements. In this process, a voltage controlled oscillator is preferred.

The LUTs are each of a very small size, for example 3 bits or five bits wide in their address for the LUTs that correct for cross talk and twice as long in address as the number of bits in the transmission medium, for example 10 bits in a processor to memory interface application running at 5 G transfers per second across a 128 bit wide interface. The delay variation can be for example 6 bits or 8 bits, so the total amount of memory need in this application is low and the area taken by this memory in silicon is tiny. Hence, a memory 3 bits wide with 6 bits of data at each address, is only 18 bits. For a 128 bit wide interface, this memory is less than 2K bits for the entire interface.

The LUTs are simply normal memory devices or structures where a short address is used to index a delay value.

The transmission medium can be any material including conducting wires, optical fibres, or any other medium. In the case of optical communications, there is negligible cross coupling and reflections can be ignored in many instances. This leaves the inherent timing errors of the driver and receiver, which can be reduced to the difference in transmission between two symbols, as well as the skew thereof. The skew in the fibre is no longer pattern dependent from data line to data line, but still requires correction. The methods used currently involve passing all possible patterns into the channel and measuring the response. The present invention makes possible a much more accurate correction based on the actual temporal characteristics of the components and their interconnect.

Operation

The operation of this system shall now be described in detail. The field of the present invention is highly specialised and therefore, the following briefing material is provided to aid the reader to understand the significance and true operation of the current invention, without prejudice or limit to the description of the invention.

The practical capacity of the channel is a function of the maximum toggle rate of the registers, the skew of the data, the variation in the clock to output delay of the transmitter and variation in the setup and hold time for the receivers.

The actual achievable toggle rate of a register or its maximum clock frequency has inherent to it a number of factors: the setup and hold time, the location and width of the phase noise distribution as well as various propagation and switching delays. If all other factors are removed, the toggle rate is the time it takes for a pulse to propagate around the gates of the feedback loop in the register. If the variations in factors such as the setup and hold time are reduced or eliminated, then the maximum toggle rate can be equivalent to between four and six gate delays. As gate delays reduce as the square of reductions in feature size, we can estimate the increase in toggle rate for registers to increase as shown in table below.

All numeric values given in these examples are given for CMOS technology, as this is at present the most widely available and lowest cost solution for the implementation of any communications channel. Other technologies such as GaAs or InPh (Indium Phosphide) have a different switching rate: their higher electron mobility will enable them to switch faster, hence toggle rates can be several times faster for the same feature size.

The primary difference between technologies, that affect the maximum rate of the communication channel using the present invention, is their relative switching speed. To scale from CMOS to, for example, GaAs at the same feature size, one need only multiply the maximum frequency of switching speed related limits by the ratio of the electron mobilities. For example, the toggle frequency of a GaAs device fabricated in a 300 nm feature size technology should be around 3.1 GHz instead of 1.1 GHz for the equivalent CMOS device. However not all the limits to switching speed scale evenly and these limits would reduce some of the advantages of esoteric materials over CMOS.

Given that the toggle rate is predetermined by the fabrication process and that the effect of variations of setup and hold time can be eliminated, this leaves the signal skew as the primary limiting factor in the capacity of a channel and it is this limit that the present invention addresses.

The following factors that determine skew are considered in the present invention:

1. Variations in the sample and hold time or clock to output time of different bits and different registers in a wide channel.

2. Impedance mismatch. As each bit passes a discontinuity, a portion of the incident energy is reflected. This changes the forward slew rate as it reduces the value of the forward voltage, and the energy thus subtracted is then added to each successive symbol in the transmission medium until the reflection is absorbed by terminating components or other damping means. Thus an impedance discontinuity causes a skew on a signal with respect to a reference.

3. Electrical noise. This has a similar effect to the impedance discontinuity in adding energy to the signal, which can either increase or decrease its momentary voltage or current, causing a change in the time for that signal to cross a predetermined threshold value used for switching. The noise has many sources and combines pink and white noise profiles.

Each one of the factors described above has an effect on the probability of a bit being received correctly. In the design of a channel these effects are analysed for their distribution and the degree of correction needed and the resolution of that correction is determined. This process will now be described in more detail.

All registers have a probability density distribution for the register being in a 0 or a 1 state as a function of the time offset of the clock to data. FIG. 8 shows the actual probability density distribution for one such register, an SSTL register: the dotted line is the closest fit of a Normal distribution, the solid line represents measurements taken at sub-pico second accuracy and resolution.

The BER contribution from a component can be measured from the timing uncertainty distribution curve for the component, such as shown in FIG. 4and FIG. . The communication channel operates with a predetermined time window around when the transition occurs.

FIG. 10 shows the time of a transition for an SSTL16857 register, measured with an accuracy of a fraction of a pico second, against the probability of the signal being latched as a 0 or a 1. The Standard Deviation on the transition point on this register is 20 ps. If this register is used in a communication channel with it latching data every 200 ps (20 ps×2×5 sigmas), the BER from this component will be 1.5×10−12. It is by a determination of this nature that the number of steps in the calibration process and the accuracy needed in that process is determined.

The BER of a single data path or line within a channel for a given data rate can be calculated by taking the timing uncertainty distribution curve for every component both along a line of a channel taking the square root from the sum of the squares of the RMS of the distributions, to arrive at a distribution curve for the line as a whole. The channel BER is the sum of the BERs of each line. The BER is one minus the integral of this curve, as tabulated in FIG. . The tighter the distribution for each component of the channel, then the lower the BER at any given frequency, or the higher the frequency at which the channel can operate.

For each of the effects that are not being compensated, the distributions are summed by the RMS of their distributions, the root is taken and an overall distribution is determined. From this the frequency at which data can be sent reliably is determined and the number of steps in the verniers is chosen.

It is necessary for the accurate and unambiguous description of the operation of the present invention to clarify what the Setup and Hold times of the registers mean.

Setup and Hold time is the total time covering all variations in the phase noise maxima from part to part, from DQ to DQ, with variations in temperature, process variation and power supply voltage plus any settling time. In a receiver the whole actual Setup and Hold period is relevant. In a transmitter the clock to data output delay is considered rather than the Setup and Hold term of the register, again with variations that arise as a result of changes of temperature, phase noise and fabrication tolerances.

Registers may exhibit true metastability where the register exhibits an exponential increase in the clock to output time as a particular clocking point is approached or they may simply exhibit phase noise. The registers in the present invention are clocked at a high speed, so whether the register is metastable is immaterial: the next clock cycle resolves the metastable state. Metastability manifests itself as phase noise in this context. See “Metastability and the ECLinPS Family” by Rennie Wm. Dover and Todd Peason, AN1504, Motorola Inc., 1996; and also “High-Speed Digital Design” by Howard W. Johnson and Martin Graham, Prentice Hall, 1993, Englewood Cliffs, N.J. 17632.

The time window in which there is a significant probability of metastability, or the time window in which there is significant phase noise in a register, is normally very small, but the variation in this time gives rise to very large brackets which are expressed as long setup and hold times or clock to output delays.

The present invention applies the phase noise to a feedback system to control the channel, ensuring it operates on or close to its region of maximal stability, this being 180 degrees out of phase from the peak of the phase noise distribution.

Use of the current invention has enabled the inventors to take measurements of phase noise distributions with accuracies of fempto-seconds and even atto-seconds. The information from this analysis is described here to explain how the calibration process used by the present invention operates.

The width of the true phase noise distribution is the comparable to the phase noise of a sample-hold function implemented in the same technology with the same charge storage, assuming all drift in that function is controlled.

A sample-hold circuit such as that shown in FIG. 12 comprises a gate driving a capacitor, followed by a buffer. The uncertainty in opening the gate is a function of the slew rate of the HOLD signal, the noise on the HOLD signal, the gain of the gating transistor and the switching speed of the gate. This effect is not metastability at all: it is simply the sampling of a signal which is undefined in time by the noise distribution on the HOLD line and gating transistor. In the case of the sample and hold circuit, the timing uncertainty comes from noise in any input buffer, noise in any command line buffer to the gate, and particularly the gating transistor switching time.

This means that when we measure the phase noise characteristics of a register, we are actually measuring the switching time characteristics for the internal circuitry that comprises the register plus input noise.

The phase noise distribution, appears to manifest a slightly less than linear reduction in the time domain as a function of reducing feature size. If one estimates the resulting function as a reduction proportional to the ratio of feature sizes to a power of 0.75, then the Standard Deviation for the timing uncertainty is expected to reduce from around 20 ps to 12 ps as technology moves from 300 nm to 70 nm.

Taking the 70 nm process, and operating with Sigma BERs, the fastest data rate that can be supported is a transition every 42 ns. This is the ultimate rate of data transmission for a serial interface with clock recovery, or for each bit of a parallel system where all skew is completely eliminated.

Operating at a higher BER would allow a higher data rate. For example using Viterbi encoding and decoding of each data line could allow the system to operate at Sigma BERs per bit in the extreme case (the data rate being half this, i.e. Sigma , i.e. one error every 200 bits—at the limit of the range that is easily correctable), which would mean the maximum data rate is a change every 28 ps, or just over 35 GHz.

In the examples shown in FIG. and FIG. 8, the time window for the register in a channel which is, for all useful purposes, free of errors, would be 210 ps (6 Sigma).

Typically, the phase noise of the register has two components: the position of its maxima, and the window around the phase noise maxima. The register without any means of controlling the position of the phase noise maximum could take data at less than 500 MHz, even if it arrived without skew.

The Operation of the present invention involves two steps:

1. Calibration

2. Data transfer.

The Calibration step uses the method as described above to determine the time delay between the transition of a clock signal and the registering of a data signal in a register, particularly register in FIG. .

The current invention implements the process described above to determine the time delays with very high accuracy, for example an application may chose to measure the time delays to ten pico-second accuracy, another very exacting application may require fempto-second accuracy.

The master state machine changes the delay within the delay vernier , to cause the data bit to switch at the correct point in time.

The use of two or more frequencies to resolve the unknown variables is evident from the above description of the method of the present invention. The change in frequency is chosen as the preferred reference means because the frequency of timing sources can be set extremely accurately in a frequency synthesiser.

Once the delay values are known for a particular combination of bits, the values are written to the appropriate LUT: the LUT depends on which variables are altered and the data pattern being generated by the state machine.

This first mode of operation is preferably carried out during the system reset phase but may be repeated. In a preferred embodiment, the LUT may have two parts, one being a non-volatile memory, the second being volatile memory, such that the entire calibration may be done only once at the end of the manufacturing process, but a fine tuning over a much smaller range is performed during power up. In some cases it is possible to perform the calibration only once, then use the calibration data throughout the life of the product.

The second mode of operation for the present invention is to send the data.

For each data word, the delay of the present bit is calculated by the master state machine applying a repetitive sequence and the symbol of interest being gated out.

It is necessary for the calibration process to first determine which symbol is which, as the delay in the transmission line is unknown at the outset. This can be achieved by various techniques, among the simplest being to send a clock signal down all data lines at a rate low enough to exceed the total timing uncertainty distribution curve with the required accuracy, for example using Sigma with averaging or Sigma without. For example, a system with a composite probability distribution for the receipt of a bit of 1 ns, could initiate the calibration process by using a data stream with an equivalent frequency of 96 MHz, using this frequency and 60 MHz not to determine the total loop delay but to set a reference edge by which all other data bits can be measured. In this manner the position of each of the bits in time in the receiver relative to the transmitter can be determined.

Once the position of a reference edge has been determined by the above process, the position of other bits in the stream can be determined by counting the clock cycles using a controlled counter and comparator, or using extra protocol information between the two state machines, or even by judicious selection of frequencies and data patterns for the calibration.

Where the access time of the LUTs is long, the transmitter register may require to include more than one pipe delay.

The vernier delays are shown in the transmitter in this embodiment, but the delays can be in the receiver and the receiver can act as the master in the calibration process.

The method of determining the time in which a transition occurs will now be explained in further detail.

Consider a channel comprising simply of a set of drivers and a set of receivers.

The timing of each drive register and receiver register is controlled by a precision Vernier delay, for example with 20 ps resolution.

The calibration procedure consists of the following steps:

1. Calibration of the Delay Verniers

2. Calibration of the Receiving Registers

3. Calibration of the Driving Registers

4. Adjustment of the Delay Verniers

In a diagram of FIG. 7, the skew measuring configuration is shown, which can be applied either to the input register (or, registers) or output register (or, registers) . A simplified diagram of skew measurement is shown in FIG. 13, where G is a Phase Locked Loop (PLL) variable over the range such as 1 GHz to 5 GHz, can be used. Phase jitter is typically less than 0.05%, and this is compensated during calibration.

All steps of the calibration procedure are based on the following skew-measuring equation:

D0

where TD is the Vernier delay, T0 is the minimum delay, τ is the discrete interval of the delay settings and N is the programmed code.

Calibration Step 1

In the first step of the calibration process, the calibration of the delay verniers , the period of the PLL is set to a value less than the interval of the delay vernier, as shown in FIG. .

Note that while a PLL is used, this does not affect the measurement. The accuracy of the PLL depends on the accuracy of the quartz crystal resonant frequency, which is typically better than 1 in 100,000, and its own noise figure of less than 0.05%. As the calibration is performed at frequencies in the 100 MHz to 10 GHz region, this tolerance created by the frequency uncertainty and by jitter is many times less than the typical 20 ps to 1 ps resolution of the regulating Vernier delay.

Calibration Step 2

The value of the vernier delay is then scanned from its minimum to maximum, sampling the output of the flip-flop many times. This allows the point at which the flip-flop has a transition to be determined. At this point, TD will be equal to the period of the generator:

D1101

Calibration Step 3

The period of the generator is then changed and the procedure described above repeated to find the next point where the flip-flop has a peak in its phase noise characteristic, that is the highest probability of the transition occurring within the register. Thus:

D2202

After this step T0 and τ can be easily calculated.

Repeating this procedure for each Delay Vernier allows all of them to be calibrated. In each measurement, there are many samples, such as 256. This increases the overall frequency accuracy by a further factor of the square root of the number of samples, for example by 16 (the square root of 256), so even a 20 ps resolution increases to a measurement accuracy of 1.25 ps overall.

Calibration Step 4

The receiving registers are then calibrated in the same way. Because the Delay Verniers are now precisely calibrated it is possible to find the difference in the timing of the peak of the phase noise for each receiving flip-flop individually.

Calibration Step 5

The driving registers are then calibrated using the previously calibrated Delay Verniers and receiving registers.

Calibration Step 6

The software compensation for differences in PCB trace lengths is added to the calibration results. This compensation uses the trace lengths taken from the actual PCB layout software and can be hard programmed or can be set in a non-volatile memory for the whole system, for example a serial presence detect memory device or integrated on the same chip as the communication channel.

Calibration Step 7

At the end of the calibration process the delays in the signals coming to a node and from the node for each bit have been measured.

The Delay Verniers can be adjusted in order to eliminate the part to part skew in the driving and receiving registers. Only the skew within the device is not compensated for, but because it has been measured it can be taken into account by the state machine software. This means that the entire system is calibrated with a total absolute accuracy of 20 ps, and relative accuracy of 1.25 ps accuracy if 256 samples are taken.

Precision registers can be used which have only a 10 ps window for the skew within the register, in which case the accuracy of the system using this technique on its own is 20 ps (the increment on the Delay Vernier). It is possible to reduce this error down to fempto second levels by oversampling, using basic sampling theory.

This process can be repeated to achieve higher levels of time accuracy, in particular when the time taken to transmit a bit is not known. This information is necessary to apply symbol by symbol selection and gating during the calibration process where this is used.

It will be appreciated that the above description and the figures are an example embodiment only and that various modifications may be made to the embodiment described above within the scope of the present invention.

CLAIMS

1. An apparatus for high speed communication, comprising: a plurality of driving registers, each driving register having a plurality of inputs and outputs, at least one output of each said driving register connectable to at least one communication line, said driving registers latching transmitted signals; a plurality of receiving registers, each receiving register having a plurality of inputs and outputs, at least one input of each said receiving register connectable to at least one said communication line, said receiving registers latching received signals; a main clock for generating a main clock signal; a reference clock for generating a reference signal for calibrating the receiving registers; said reference clock being associated with said main clock; a first set of phase shift means associated with said plurality of driving registers, for the relative alignment of the driving registers' timing within the plurality of driving registers.

2. The apparatus according to claim 1, further comprising a common transmission line of known signal propagation rate for supplying the said reference signal.

3. The apparatus according to claim 2, wherein each of said receiving registers is connected to said reference clock by said common transmission line of known signal propagation rate.

4. The apparatus according to claim 1, wherein each of said phase shift means is pre-calibrated by varying a calibration frequency.

5. The apparatus according to claim 1, wherein said phase shift means comprises at least one of: a variable delay, a programmable delay, an analogue vernier, a digital vernier.

6. The apparatus according to claim 1, wherein each of said receiving registers for latching signals received from said communication line is pre-calibrated by determining a minimal feasible time delay between the reference clock edge and a moment when the register latches data.

7. The apparatus according to claim 1, further comprising a second set of phase shift means associated with said plurality of receiving registers, for relative alignment of the receiving register's timing within said plurality of receiving registers.

8. The apparatus according to claim 1, further comprising a storage means for recording and storing information on skew in a communication media, for at least one data pattern transmitted through the communication line.

9. The apparatus according to claim 8, further comprising a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above skew.

10. The apparatus according to claim 1, further comprising a third set of phase shift means associated with said pluralities of driving and receiving registers, for relative alignment of the register's timing between said pluralities of driving and receiving registers, said pluralities of registers being connected to the main clock via said third set of phase shift means.

11. The apparatus according to claim 10, wherein said third plurality of phase shift means comprises at least one shift means associated with each of the said pluralities of driving and receiving registers.

12. The apparatus according to claim 1, wherein the driving registers and receiving registers are interconnected so that outputs of driving registers are connected via respective communication lines to the inputs of respective receiving registers to calibrate said plurality of driving registers.

13. A method for reducing timing uncertainty of a communication apparatus, comprising: calibrating a plurality of receiving registers of the communication apparatus using at least one set of programmable delays, each of said receiving registers being connectable to at least one communication line, in relation to a reference clock edge; calibrating a propagation delay of a plurality of driving registers of the communication apparatus, each of said driving registers being connectable to said at least one communication line, using the calibrated receiving registers; and performing relative alignment of the programmable delays to a main clock edge.

14. The method according to claim 13, further comprising calibrating a respective programmable delay for each receiving register before calibrating the receiving registers.

15. The method according to claim 14, wherein the programmable delays are pre-calibrated by varying a calibration frequency and fixing the difference in time of the two transition moments.

16. The method according to claim 13, wherein the accuracy of at least one of calibration of the receiving registers and calibration of the driving registers is increased by determining for at least one of the receiving and driving registers, a minimal feasible time delay between the reference clock edge and a moment when at least one of the receiving and driving registers latches data.

17. The method according to claim 16, wherein the determination for minimal feasible time delay is performed twice, once for the falling edge of said reference clock, and again for the rising edge of said reference clock.

18. A method according to claim 13, wherein the propagation delay of each of the driving registers is calibrated by varying delays to best match an output transition with a latch time of at least one of said receiving registers.

19. The method according to claim 13, wherein the propagation delays are calibrated for each individual bit of the receiving register data.

20. The method according to claim 13, further comprising transmitting of data through the communication line provided by at least one driver and measuring a skew for at least one data pattern transmitted through the communication line.

21. The method according to claim 13, further comprising recording and storing information on skew in said at least one communication line, for at least one data pattern transmitted through the communication line.

22. The method according to claim 21, further comprising generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the stored skew information, so as to compensate the above skew of the communication line.

23. The method according to claim 22, wherein the information is stored on skew caused by inter-symbol interference in the transmission media.

24. The method according to claim 22, wherein the information is stored on skew caused by cross-talk influence in the transmission media.

25. The method according to claim 13, wherein said receiving registers are calibrated with reference to a periodic reference clock edge.

26. The method according to claim 13, wherein at least one of the calibration of the receiving registers and the calibration of the driving registers is partially or completely computer implemented.

27. A computer readable medium including a computer readable program means for implementing or simulating hardware functions of a communication apparatus comprising: a plurality of driving registers connectable to at least one communication line, said driving registers latching transmitted signals; a plurality of receiving registers connectable to said at least one communication line for latching signals received from said communication line; a main clock for generating a main clock signal; a reference clock for generating reference signals for calibrating the receiving registers; said reference clock being associated with said main clock; a first set of phase shift means associated with said plurality of driving registers, for the relative alignment of the driving registers' timing.

28. A timing uncertainty reduction system for calibration of a high speed communication apparatus, comprising: at least one driving register for latching transmitted signals, each said driving register having a plurality of inputs and outputs; at least one receiving register for latching received signals, each said receiving register having a plurality of inputs and outputs; a main clock for generating a main clock signal; a reference clock for generating a reference signal for calibrating the receiving register or registers; said reference clock being associated with said main clock; and a first set of phase shift means associated with said driving register or registers, for the relative alignment of the driving signals' timing.

29. The system according to claim 28, further comprising a storage means connected to said at least one driving register or at least one receiving register for recording and storing information on timing uncertainty in a communication media, for at least one data pattern transmitted through the communication media.

30. The system according to claim 29, further comprising a plurality of adjustment means for generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the information stored in the storage means, so as to compensate the above timing uncertainty.

31. The system according to claim 29, wherein the information on timing uncertainty is stored on skew caused by inter-symbol interference in the communication media.

32. The system according to claim 29, wherein the information on timing uncertainty is stored on skew caused by cross-talk influence in the communication media.

33. The system according to claim 30, wherein the correction is applied using said first set of phase shift means.

34. The system according to claim 30, wherein the correction is applied using a second set of phase shift means associated with said plurality of receiving registers, for relative alignment of the receiving register's timing within said plurality of receiving registers.

35. The system according to claim 28, further comprising a common transmission line of known signal propagation rate for supplying the said reference signal.

36. The system according to claim 28, wherein each of said receiving registers is connected to said reference clock by said common transmission line of known signal propagation rate.

37. The system according to claim 28, wherein each of said phase shift means is pre-calibrated by varying a calibration frequency.

38. The system according to claim 28, wherein each of said receiving registers for latching signals is pre-calibrated by determining a minimal feasible time delay between the reference clock edge and a moment when the register latches data.

39. A computer program product for implementing a method of reducing timing uncertainty of a communication apparatus, said computer program product comprising a computer usable medium having computer readable program code means embodied thereon, said computer program code means comprising a computer readable program code means for causing a computer to perform transmitting of data through at least one communication line provided by at least one driver and measuring a skew for at least one data pattern transmitted through the communication line; a computer readable program code means for causing a computer to perform recording and storing information on skew in said at least one communication line, for at least one data pattern transmitted through the communication line; a computer readable program code means for causing a computer to perform generating and applying a correction to the timing position of a signal transition between two logical levels, the correction being generated on the basis of the skew information of the communication line, so as to compensate the above skew; a computer readable program code means for causing a computer to perform calibration of a plurality of receiving registers of the communication apparatus using at least one set of programmable delays, each of said receiving registers being connectable to said at least one communication line, in relation to a reference clock edge; a computer readable program code means for causing a computer to perform calibrating a propagation delay of a plurality of driving registers of the communication apparatus, each of said driving registers being connectable to said at least one communication line, using the calibrated receiving registers; and a computer readable program code means for causing a computer to perform relative alignment of the programmable delays to a main clock edge.

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